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					 LiteX - an open source FPGA front end
					
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				BigEd  | 
				4  | 
				36601  | 
				
					 Wed Feb 12, 2025 6:51 pm 
					BigEd
						
					 
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					 Minimal presettable counters
					
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				enso1  | 
				0  | 
				27924  | 
				
					 Sun Sep 29, 2024 9:35 pm 
					enso1
						
					 
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					 Help/Critique for a design with an ATF1508 CPLD
					
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				DoctorWkt  | 
				5  | 
				29965  | 
				
					 Thu Aug 31, 2023 10:40 pm 
					DoctorWkt
						
					 
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					 Floating Point Library
					
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				robfinch  | 
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				46576  | 
				
					 Tue Feb 22, 2022 3:12 am 
					robfinch
						
					 
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					 Noc - Network on chip
					
						  [  Go to page: 1, 2 ]  
					
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				robfinch  | 
				24  | 
				74927  | 
				
					 Mon Jan 03, 2022 9:13 am 
					robfinch
						
					 
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					 Making wide(r) memory from byte-wide memory?
					
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				tingo  | 
				4  | 
				16118  | 
				
					 Mon Dec 14, 2020 8:50 am 
					tingo
						
					 
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					 Resources for Newbie Verilog and VHDL People
					
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				DoctorWkt  | 
				13  | 
				40474  | 
				
					 Tue Jun 16, 2020 9:33 pm 
					quadrant
						
					 
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					 clock division w/ CPLD
					
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				shoggoth  | 
				3  | 
				18684  | 
				
					 Fri May 08, 2020 6:08 am 
					BigEd
						
					 
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					 programmer mode bug in quartus 9.0 (altera)
					
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				oldben  | 
				3  | 
				15084  | 
				
					 Thu Dec 26, 2019 10:46 pm 
					oldben
						
					 
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					 How do I determine when SRAM is ready from a CPLD?
					
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				cbmeeks  | 
				4  | 
				19122  | 
				
					 Sun Aug 04, 2019 5:05 am 
					barrym95838
						
					 
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					 Verilog code review for 8-bit computer
					
						  [  Go to page: 1, 2 ]  
					
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				fmahnke  | 
				18  | 
				60145  | 
				
					 Wed Feb 20, 2019 9:25 am 
					BigEd
						
					 
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					 TOYF (Toy Forth) processor
					
						  [  Go to page: 1 ... 4, 5, 6 ]  
					
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				Hugh Aguilar  | 
				78  | 
				144746  | 
				
					 Fri Nov 09, 2018 8:14 pm 
					Hugh Aguilar
						
					 
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					 j68 - a 68000 implemented on a forth microarchitecture
					
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				BigEd  | 
				9  | 
				40987  | 
				
					 Fri Mar 02, 2018 6:39 pm 
					NorthWay
						
					 
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					 65ISR
					
						  [  Go to page: 1, 2, 3 ]  
					
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				Hugh Aguilar  | 
				35  | 
				75420  | 
				
					 Thu Oct 12, 2017 4:10 am 
					Hugh Aguilar
						
					 
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					 Seeking the smallest 68000 implementation...
					
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				BigEd  | 
				8  | 
				39515  | 
				
					 Tue Sep 19, 2017 5:45 pm 
					BigEd
						
					 
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					 The ZIP cpu - a pipelined RISC
					
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				BigEd  | 
				0  | 
				15271  | 
				
					 Mon Sep 11, 2017 2:28 pm 
					BigEd
						
					 
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					 Ben Eater's SAP inspired computer implemented in VHDL
					
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				Xark  | 
				3  | 
				18128  | 
				
					 Fri Aug 25, 2017 3:03 pm 
					BigEd
						
					 
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					 xr16 - a tiny RISC, with CPU design tutorial and SoC design
					
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				BigEd  | 
				0  | 
				15464  | 
				
					 Mon Jul 24, 2017 12:16 pm 
					BigEd
						
					 
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					 Tactics for small and fast FPGA implementations
					
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				BigEd  | 
				2  | 
				15629  | 
				
					 Fri Jul 14, 2017 5:11 pm 
					BigEd
						
					 
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					 Parallella, $99 "Linux Supercomputer" (with FPGA)
					
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				BigEd  | 
				7  | 
				27791  | 
				
					 Thu Dec 22, 2016 9:19 am 
					BigEd
						
					 
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					 A Forth CPU on FPGA for homebrew GPS
					
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				BigEd  | 
				2  | 
				17109  | 
				
					 Wed Nov 09, 2016 4:58 pm 
					BigEd
						
					 
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					 Multi-port Memory Controller
					
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				robfinch  | 
				4  | 
				18644  | 
				
					 Thu Apr 28, 2016 4:22 am 
					robfinch
						
					 
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					 Small FPGA CPU
					
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				Arlet  | 
				11  | 
				28975  | 
				
					 Wed Dec 09, 2015 4:42 am 
					Arlet
						
					 
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					 Clock Wars
					
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				robfinch  | 
				5  | 
				20777  | 
				
					 Fri Feb 06, 2015 9:41 am 
					robfinch
						
					 
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					 Propeller 2 on FPGA
					
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				BigEd  | 
				0  | 
				13581  | 
				
					 Sun May 25, 2014 10:59 am 
					BigEd
						
					 
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