What are the specs for your text mode video controller? How many columns and rows? Is it fixed formats only? Does it support color? Does it use main memory or dedicated memories? Does it use a custom chip?

Hello,

Allright, for my first post here, I'll jump in.

I made the video controller for my 8088-based breadboard computer:


It all fits nicely on the seven breadboards on the right.

It is based around a HD6545, a somewhat improved version of the venerable 6845 CRTC. It is also a bit faster which allows me to use a 25.125MHz pixel clock.
With this clock, the supported resolutions are all 640 pixels wide by either 400 or 480, that means all modes are 80 columns. I could use 640x350 as well, but my monitor doesn't seem to like it

The characters are stored in a 32k static RAM, populated from the BIOS during boot. A register lets me set some high order bits of the address in order to select between four banks of characters. This chip is mapped at address 0A0000h.

Display memory consists of two 32k static RAM chips, arranged in a even/odd configuration as seen by the CPU, much like usual PC text mode: character code at even addresses, with their color attribute in the next byte. These are mapped at address 0B0000h, and most video modes will look for display data at 0B8000h, just like on color adapter on PCs.

All three SRAM chips are CY7C199-12 because they were fast and easy to get.

Access to the charmap or to display memory from the CPU will pause the CPU by pulling the \WAIT line low if the adapter is not in a retrace period (either vertical or horizontal). That wait-state generation circuit is not perfect though, and the leftmost two characters can often show "snow" during updates.

A bunch of 74ALS257 2:1 multiplexers will select between CPU access and VDU access to the RAM chips.

Sixteen colors are supported. Again, just like PC color modes, the low nibble of the attribute byte is for the foreground color, high nibble for the background color.

The RGB signals are generated by a IMS G178 palette DAC, which makes them configurable. But these chips are either very finnicky, or slowly dying, and I often have to resort to a simple resistor DAC to debug things when the screen goes black or when the colors all go weird

By reprogramming the CRTC and updating the character RAM, it is fairly straightforward to configure text modes of 25, 30, 50 or 60 lines: that is 640x400 or 640x480, with a character height of either 16 or 8 lines.

I can also configure it so that characters are two lines high, and with even scanlines read from address 0B0000h while odd scanlines are still read from the usual 0B8000h. This makes some kind of graphical mode, with the limitation that each group of 8 pixels must share the same two colors (the foreground/background pair). This mode is limited to 640x400b though, because 640x480
wouldn't fit into the memory. I later discovered that the CGA adapter uses a similar trick for its graphics mode

Hope you like it !

Oh, that's nice!

I have several different versions of a text controller, tailored to different projects, differing mainly in the color support and bus interface. The controllers are written in Verilog and run on an FPGA. The guts of the text controller is completely programmable in a manner similar to a 6845. But it inputs sync signals instead of generating them. It does have default settings so there is no need to set registers. The screen can be up and working without cpu intervention. There is a reset triggered screen randomizer that fills the screen memory with random data so the display is not blank at reset. The controller for the rfPower-SoC defaults the screen to 64 columns by 33 rows of characters. This is a setup for 800x600 VGA resolution where characters are 12x18 pixels. The size of a character and the size of the pixels is completely programmable. A character cell is 32-bits. 12-bits for the character code and 9-bits each for the foreground and background colors (RGB333). The remaining 2-bits control the graphics plane or z-order. The controller is meant to be inserted into a video pipeline and has both video input and output. This makes it possible to overlay the text screen on top of a graphics screen by using a transparent color for the text background color.
The video pipeline starts with the frame buffer, then the text controller, then the sprite controller. The video data signal is output by one controller and input to the next. The data format is ZRGB(8,8,8,8) where the Z stands for the Z-order or graphics plane. Usually the Z-order is truncated to fewer bits. The text controller has only two significant Z bits for instance. The Z-order allows the pipeline to determine which pixels are at the top.

Added a PCI style config space to the text controller, allowing the IO addresses for the controller to be altered programmatically.