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Oh yeah, while at it, having separate MMUs for instructions and data -
Separate MMUs for instructions and data is an interesting idea. The page table entries could be made specific for instructions or data. Might not need all the access rights for each type, so could conserve bits. However, it may be more resource efficient to have just a single MMU.
There is just a single 128-bit bus connecting the core to the outside world, and the MMU is attached to this. It could possibly tell the difference between code and data, and manage each separately.
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Sketched out a 68k design using 20-bit instruction parcels. This allows for 16 data and 16 address registers. It also allows an additional operand size ‘.O’ for octabyte. The instruction set remains much the same. Branches have 12-bit or 20-bit displacements available. Added a CLRM – clear multiple registers instruction.
This was mainly just an exercise, no plans to implement. Got me started thinking about RiSCV and implementing a clear multiple registers with that processor. It could be done using a two-deep register file where one depth always contains zeros. When a register is ‘cleared’ the depth pointer could be incremented to point to a zero value on read. When a register is written the depth pointer could be decremented so the actual value is readable.
This would be using the LUT ram to multiplex a zero to the output when the register is clear.
A bitmask could be used to clear selected registers by or'ing the mask with the depth pointers.
