I had a chance to play with Delta-Sigma code and it looks like it would apply some nice dithering to your LSB.
For testing I used only a single bit for each colour with no kind of external DAC, the only added components are a 1K + 270Ohm series resistor net (1 per R,G,B) to drop the 3.3v output to 0.7v for the VGA input of the screen.
I used an internal colour space of 18 bits (6 per colour). 50MHz pixel clock with a 300MHz subpixel clock. Used a little Altera Cyclone II board that could do with VGA, seems to have a nice PLL.

Video:
https://www.youtube.com/watch?v=Sfqd7RtJZ_s

Code looks like this, excuse the VHDL


I've only had a quick look at the source so far so might have missed it. The ability to average two bitmaps is handy but I don't think I saw it in the code. It would help with the datkening areas of the screen : (bitmap1 colour + bitmap2 colour) / 2

I'll be changing that 'ADD' into 'AVG'. I've read that the simple raster-ops AND,OR,XOR, aren't actually that useful, and that higher mathematical functions are usually used instead. For example for lighting effects. I wonder if the blitter could be treated more like a matrix accelerator co-processor to the cpu. I've set it up as if there were 64 "matrix" (image) registers, with operations taking place between the registers.
One thing I've left out of the blitter so far is a shifter / rotator. A shifter / rotator is usually used to align source pixels with the destination. However it would be difficult to do as pixels are not byte aligned in this case and are packed into 128 bit strips. Instead I have the blitter just working a pixel at a time. That may make the blitter quite slow compared to other solutions. The blitter gets more efficient at greater color depths however.

Started working on another processor project called DSD1 (for Darkstar Dragon 1). There are a couple of things I desire which FISA64 doesn't support.
- segmented architecture
- condition codes
- variable length instructions

Variable length instructions are a good way to make better use of the instruction cache. Varying the instruction length with shorter instructions as opposed to a fixed 32 bit format, can result in an instruction stream significantly smaller. That means fewer cache loads and higher performance.

For any operation performed by the processor there is a result and additional result status data. For many cpu's the result status data is stored in a condition code register(s).

A segmented architecture offers a low-overhead means of performing memory management.