Interrupts are checked on instruction fetch. The currently executing instruction adds to the latency, so it could be 40 cycles + interrupt handler cycles.

I'm thinking more efficient address generation is worth the cost. Hopefully there will be enough spare microcode control lines to include an address adder.

How fast is the clock? If it is fast enough having greater latency may not be an issue. For instance, at 10 MHz the instruction can take 10x as many clocks and still have the same latency as at 1 MHz.

Clock will probably be around 4Mhz. So around 10us latency. Going with individual push/pop instructions will be slower but will decrease interrupt jitter.

I've been thinking about ditching interrupts, as polling probably makes more sense for a peripheral processor.