Amazing! Done amazingly fast too.

No slow, I had the one bug that takes up the other 90% of the debugging
time. Now that I have most of my ideas developed and bug free, I am redesigning my 9 bit
cpu from a few years ago.

Ben.

I will take over the word, my cpu is a bit (1) better than any 6502,
after I change may name to Ben Gates.

Ideas from the 9/18 bit cpu, gives me a simple 20 bit cpu.

The original goal was a 6800 stretched to 18 bits, in the 1974-1977 time
frame, with the concept bytes need to 9 bits, so you don't lose addressing
space over a word addressed cpu as well as 8 bit opcode limits what operations
you can do. Expanding to 20 bits lets me now use a 2901 bit slice.

The PDP 8 has emulated floating point, and a floating point trap is added
to my instruction set. This will give me REAL numbers, so I can have a ALGOL
type language. Thinking how this would compete with a real PDP8 price wise
(memory was $$$ but dropping in price) 20 bits gives me the best value for the money over a 12 or 16 bit cpu.
The use of Dual 8" floppy drive with GCR would give me a low cost system,
compared to DEC and 25% more over a CP/M system in 1976.

All the changes, lets me use cheap 72 pin .156" card edge connectors to make a simple
mother board, compared to bigger projects with more connectors.
SDC cards, fake dual floppies drives.
Ben.

I have been designing too early ~ 1975. I need to wait untill ~ 1977, just after the APPLE I.
By then 16K drams were out, and early FPLA's like the 82S100 as well as the 2901 bit slice and 512x8 proms.
Using them I can cut the data path to 4 chips per 4 bit slice (25+glue) and about 25 chips for the control logic. I have gone to a 24 bit computer because that is next standard size for problem solving, rather than a bigger address space. Cards will be on a mother board with S-100 style
connector, and about a S-100 card size for 16Kb x 24 bit memory,
48Kb for programs and 32Kb for the OS. The OS is rather small, just that ~ 12K is for Disc and
4Kb stack. 200ns ram lets me have 6.144 MHZ clock. 8" floppies with unknown a GCR will
give me 6Kb (1K blocks) per track ~462K per disk.
Ben.

I am dropping the 16/32 bit CPU as it is too big a project, as well as the 20 bit cpu.
The 24 bit cpu wil use core style timing, and all the pins on the S100 bus connector.
BDP ( Ben Data Processor ) will have 48Kb of memory, with 768 byte disk blocks on
DSSS 8" floppies. 76 tracks with 5 sectors / track GCR. ~ 530K per floppy. 1.5 us Memory
cycle.
Data Path 5 chips per 4 bit slice+ glue.
Control Path 5 22v10's , 74ls161/74ls163 counters +buffers + glue.
19 bit addressing. Opcodes similar to the 9 bit cpu, but 7 registers+ PC.
Ben.

Is the 768 size disk block because of the use of 24 bit values? It would seem more natural for disk blocks to be 512 or 1024 bytes.

I would guess it's 256 words.

I read /write 3 256 x 12 disk block from the SD card, with 0's to pad the 16 bit words.
4 blocks make a disk sector of 768 12 bit bytes. block number = sector << 2.
This lets me emulate 8" floppy drive
with 76 tracks and two heads. I use a FAT table disk format and 760 sectors per disk.
Disc Buffers take up most of 16Kb I have reserved for the OS. I still have wire in the 2
Arduino SD (standard) shields to the FPGA expansion bus. I have lots of cheap chinese
SD cards to use as floppies. ~ 520Kb per floppy make a usable development system.
$2 floppies and $10 drives VS $20 floppies $1K drives of the 1970's.
Ben.

Ah, I see: you're using 12 bit bytes, but necessarily padding into 16 bits to access an SD card. Makes sense!

That is an interesting mish-mash of old and new technology. Using the SD cards as floppies to emulate 8” disks, wouldn’t that leave a lot of space on the SD card unused? Could they be partitioned like a hard-disk?

For that era mass media was rather sparce, 8" floppies or the RK05 hard disk @ 1.6MB.(DEC)
As the goal here is a small computer, a RK05 is out of place. RK05's were for UNIX.
A 8" floppy about $1,200. RK05 about $8,000. A 16 meg SD covers most removable media from
that era.
Ben.

Revised to add R++ and --R to the instruction layout of the 32 bit cpu
with a 2901 ALU. The new BIOS now can load a bootstrap
from the serial port, but disk I/O needs to be revised for the new hardware and system jmp tables moved. One meg of address space is reserved, giving me a DOS dual floppy like computer system.
Ben.

1MB of address space is a lot for 1976. At 32 bits is this a mini/mainframe equivalent?
R++, --R address modes are hard for a compiler to use.

I am tempted to try a come up with a TTL based computer myself. But then I think: someone already did this and for what I'd want it would be a whole cabinet of electronics. Still it might be fun.

More often called POP and PUSH if R is the Stack pointer.
The design more a Mini-computer for the simple reason I have no MMU and Floppy Style Drives.
I have been using several 22V10 PALS to simplifiy control decoding, that replace 5 or 6 TTL compnents per PAL. 82S100 FPLA's would have been used in the 70's time frame.

Found several bugs in the microcode, mostly cut and paste errors as I revised the Instruction Order Codes. It seems now to be working as 3 chip err card cpu, proving that a 32 bit cpu could
be home built design, providing one had the money as it is 4x the cost of 8 bit cpu.Disk Block size is 1Kb blocks so I could run FORTH. No C compiler prevents me from doing a small Unix style OS.
Ben.