Well it was working until the MAX232 exploded. You have 3 versions, MAXIUM ,TI , CLONES.
The schematic was for TI, and I had the other brands.

Added a few more bypass caps, and fixed the bootstrap.
Bootstrap and memory now seems to work again. Not sure why with all the changes.
/TEST
* 200
LD A #0123457
HALT
..1 .1. .11 1.. 1.1 111

The CPLD's seem to very sensitive in routing correctly, and I need to
do more testing.

Dr. Emmett Brown: [Marty is showing Doc Brown the flux capacitor in the DeLorean time vehicle]
[5:1:57]
Dr. Emmett Brown: It works! It works!
[grabs Marty]
Dr. Emmett Brown: I finally invent something that works!

Fixed a few more bugs, with the logic ATF1508. Added in a few more bypass caps.
Close to having a design with the features I want, but IRQ service logic is untested.

I started around 2004 with TTL paper designs, but never got anywhere.
I planned on using CPLD's but later changed to a FPGA development system.
This wasted a good 20 years, as the hardware had too many routing issues.
The last project using pals and 2901's did not work, as it had memory problems
running programs like the serial bootstrap or front panel logic.

A defective MAX 232 was crashing the system, as it was a power supply hog.
This may have been one of the reasons the last computer did not run
as well as no power and ground planes.

Tomorrow I plan to test if byte addressing works, and shift logic.

Byte and shifting did work.
Direct memory access did not, do to a decoding error on the index.
Revised the memory card PCB to have write protect on the eeprom,
and they will be in next week.
Found a way to get .6 us half cycle, so I now have PDP 8/E core memory speeds.
Still need to revise the baud rate clock to divide by 85 rather than 64.

Revised the timing on the ALU card.
Well Now I have a 1.5 uS memory cycle time computer.
Basic timing in micro seconds. A direct/indexed instruction
seems slower since most computers had short indexing form,
but often needed indirect addressing for a longer memory reference,
JCC is 1 cycle longer to display ac/pc for the front panel.

1.5 ctl,shifts
2.25 reg operate
3.0 exg, memory ref auto , jcc false
3.75 lea
4.5 jsr , memory reg indexed
6.0 jcc true

Looking the printout for timing, lea has typo bug.

Waiting for a new memory card PCB, with better bypass caps
and write protect switch.
Now looking for memory test algorithm, as I have most opcodes
tested.The rest of this week will be stealing Halloween candy and
working a compact flash, timer io card pcb.

I simplified my alu data paths, and lea is not possible any more.
Having lea as unused opcode (for now) I changed the small C compiler
not to use LEA. JPA is now a option, as a indexed Jump.
- FAST BREAKING NEWS- NEXT is now implemented. I can port FORTH,
but not tonight.
Just need to check the alu decoding and I am done.

I got side tracked by a pcb layout, for compact flash.
My new memory PCB's are expected Monday, Then I will be ready
for some power testing. Using CPLD's to interface lets me keep the layout
simple.
The only thing VIRTUAL about this project is my money, It comes and goes.
(mostly on small things like bypass caps).

Finalized the instruction set, added swap memory instead of lea. Set the console bootstrap
to be 8 None 1 stop 1200. baud. It is good thing that the bootstrap in in the CPLD, as some
how the EEprom got corrupted. Can't wait for the new memory pcb's as it has a write protect
switch. Set the starting address to 192 (300 in octal) so I have bit more space for internal
global variables and tables. Perhaps I might end up with a CP/M style os.

Some minor revisions.
A) Late 1969 concept
using 2 bit adder and 16x1 ram for a bit slice design.
CPU in one rack box
MEMORY 64K max per rack box
IO 1 rack box per device type

B) 2 us Core Memory cycle time
C) Reading of front panel switches

I need now to work on a blinking light demo.
edit
I have now a simple 2 am light demo.

Are you planning a 1969 computer with 1969 parts?

3 74H04's, and few NXIE tubes are all the 69 parts left in my junk box..
The 555 timers came out in 1972.

This design with the front panel, while not as complex as the PDP-11
it still is more complex than a PDP-8. A 256x16 diode rom is needed
for decoding at least, and modern (1969) TTL is used.

This is as early as one could build this design.and fits well with
trends at that time, general purpose registers, a stack, byte sized operands
and immediate data, All of my other designs mostly based off a extended
6800. This is more my simplified version of a PDP 11 extended to 18 bits.

The current logic design while using CMOS programmable logic,could have
come out say 1986 using similar parts. The main reason I have a working
product is cheap PCB's and a way to program stuff like the CPLD's.
I was trying for several years to fit a this into a FPGA but the logic never routed
well.

Today I plan to install the new memory cards,and then I can start writing software
for memory testing.
The compact flash card PCB's are in but am waiting for a few last minute parts.
If the new cards work well, I will have a working 1969 computer of sorts.

Well one of the new cards is a dud?
I got more PCB's, but I have to wait till Tuesday
for more sockets. Had to rollback to a earlier
version. Removed swp,exg,lea and front panel swr read.
(now NOP's). Need to fix the rom stuff. Just
to complex for 1969.
The good news is the Cycle time is now 1.6 uS.

Thinking it over, since the logic design is based on a a simple micro code
rather than state decode,I have no choice but to have the initial release around
1974.
The computer will have 1 card for control decoding, and two 9 bit cards
for the alu. 4 bit wide parts will be used as 3 bit parts to have a 9 bit data path
if it was built in 74.
~1.6 us memory cycle time because it makes for easy serial timing,on the replica.

Implemented all the instructions I want but LEA for some reason just loads zero.
LEA is optional instruction I may drop, for load switch register.
More testing for the next day.

Well after the midnight snack. I found the LEA bug, a encoding problem.

I need a better front panel, so I can test better with easy to read octal.
I have whole bunch of hexadecimal TIL311's for this.