Last visit was: Thu May 01, 2025 12:19 pm
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It is currently Thu May 01, 2025 12:19 pm
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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Quote: I decided to try porting Dunfield's C compiler, for my cpu.
That's a good one to adapt. I got a copy of a derived C compiler source code after purchasing a book. Which CPU was it for? It was a 386 version that I tried adapting to the 68000. I have the source code for the MMURTL OS that I have studied some. The issue with a lot of OS is they are large, with a lot of pieces to them. I have been working on one myself from time to time that I have had limited success getting to work. The latest kernel is about 9kB, but does not do too much. I have gotten as far as getting simple task switching working. I had keyboard input and text output working and could abort programs with ctrl-C. But that was a while ago. I keep switching processors so I do not have a stable environment to be able to get it working. One can do a lot with a decent macro capability. Speaking of running out names, I swear I am going to start just numbering them. CPU1, CPU2, .... _________________Robert Finch http://www.finitron.ca
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| Mon Apr 14, 2025 4:55 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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Other the word aliment needing to be on even addresses I don't see any problems so far.
If possible have your machine be able handle data not on word boundaries, that
is biggest issue other than endian when porting something.
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| Mon Apr 14, 2025 8:57 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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Decided to add flags, this gives me the CMP instruction.
Needed to use the last free pin, on the CPLD for the alu sign bit.
------
Total dedicated input used: 4/4 (100%)
Total I/O pins used 64/64 (100%)
Total Logic cells used 125/128 (97%)
Total Flip-Flop used 43/128 (33%)
Total Foldback logic used 5/128 (3%)
Total Nodes+FB/MCells 131/128 (102%)
Total input pins 32
Total output pins 36
-----
I hope I have no errors in the control sections
as I have no room left in the CPLD.
REGISTERS ABCD update the flags. INDEX REGISTERS WXYS can be tested
for zero/non zero but does not change flags. Shifting always sets the flags.
Op 4 (with carry bit) sets the ZF true if alu eq to zero and the ZF is true.
This I hope will make 36 bit long data TESTING practical.
LEA X' ? #
OP A X'+
OPC B X'+
Flags are updated for long data.
Hardware mods are in, I just need to burn the new control CPLD.
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| Wed Apr 16, 2025 6:33 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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Had to rethink how I checked the conditional logic for testing. Changed the compare logic to a true compare
and I need to revise conditional testing in what little software I have. The order code is mostly finished.
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| Thu Apr 17, 2025 8:34 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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Gone back a revision, so I can have a more PDP 11 like decoding, with a indirect mode.
Lots of changes needed in the software, so it will be a good day before I can test the new code.
... Later in the day
Only a partial success. I only have space for register auto indirect with the microcode I have.
Standard instructions are working, but I have not tested auto indirect yet.
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| Sun Apr 20, 2025 8:20 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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Had the wrong version being edited, and only partial microcode had been added.
I have the microde in, but now I ran out of day to test the new stuff.
All my opcode holes have been filled, so I suspect other than a few tweaks I want to try
I am done. This clam is happy, but hungry.
Footnote: the clam is now fat. The tweaks had too may mods so the software crashed.
129 out 128 macrocells used.
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| Tue Apr 22, 2025 2:26 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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My home brew computer seems to be working but my windows 10 computer is acting up, it is in check disk start up loop. I just can't have a 2 computer household. I was hoping to have a jump or branch for conditional logic,but that did not workout. All other features I wanted for 18 bit data is in,but no microcode room for long instructions. About 1/2 a PDP 11 or 1/4 a PDP K. https://gunkies.org/wiki/PDP-KBen. PS: Both the PDP 11, PDP K look overly complex.
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| Wed Apr 23, 2025 3:45 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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I thought of alternate way to do branches, but it has a bug in the code.
I need more testing, but my pc is down.
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| Wed Apr 23, 2025 8:57 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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Trust windows. Ya.
Drive E failed and but it just wanted to check C:
Found more bugs. No bug free code here, they have to pay!
Most of my time was figuring how to do a 74XX181 version vs the CPLD one.
The only really rare part is 74ls399 2/1 storage register,
Changed a register swap for a negate. The control section will use PAL's
and EEROMS. April 74 is the projected release date.
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| Sat Apr 26, 2025 10:26 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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Need to change a counter from down to up.
Timing looks just possible for TTL with the slow ram/rom of the time.
74 and 74S gives me OK timing for back then,
For today I need to use 74LS and 74F parts with 7.38 MHz clock, divided by 6.
Since I don't have TTL dual port memory, I have to write the IX register to the I/O
bus and read it back in, for AC = AC op IX. This removes any option for LEA or Register swap.
Simple decoding removed a few other instructions.
Microcode is rather generic in decoding, so it is complete regardless of the alu logic used
so the only thing needing to be burned is the 2 256x8 control proms if I build a TTL version.
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| Sun Apr 27, 2025 4:32 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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The current ALU board. CONTROL 1508 Code: *
18 bit small computer
This is a generic micocode source a 18 bit computer with
byte addressible memory.
This part is microcode assembler (micode.exe)
*
@ // enter CPLD logic compiler
/*
18 bit small computer
This is a generic micocode source a 18 bit computer with
byte addressible memory. This part contains the pal logic
and the rom lookup tables. A 74181 cpu card would use a 32x8
prom to convert for the correct bit patterns.
CPU model
18 9 1
+---+---+---+---+---+---+
| : | 0 A GP A/Z
+-----------------------+
| : | 1 B GP B/B
+-----------------------+
| : | 2 C GP C/C
+-----------------------+
| : | 3 D GP D/D
+-----------------------+
+---+---+---+---+---+---+
| : | 4 W IX #/W
+-----------------------+
| : | 5 X IX
+-----------------------+
| : | 6 Y IX
+-----------------------+
| : | 7 S IX
+-----------------------+
+-----------------------+
| | 4' PROGRAM COUNTER
+-----------------------+
1
+-+
| | SF SIGN FLAG SET IF MINUS / A,B,C,D
+-+ OR SHIFT FLAGS
+-+
| | ZF ZERO FLAG SET IF ZERO / A,B,C,D
+-+ OR SHIFT FLAGS
+-+
| | CF CARRY FLAG SET IF CARRY / A,B,C,D
+-+ SET ON SHIFT OUTPUT
OR SHIFT FLAGS
ALU FUNCTIONS AC IX IX[ SHIFT
# OPCODE FUNC
0 ST STORE A A Z 0
1 ADD/ADC ADD B B B 0
2 SUB/SBC SUBTRACT C C C C /SRF
3 CMP/CPC COMPARE D D D S
4 AND AND W #/W W 0
5 OR OR X X X 0
6 XOR XOR Y Y Y C /SLF
7 LD LOAD S S S S
876 543 210 987 654 321
+---+---+---+---+---+---+
|1UO|OOO:AAA|32B|XXX:+##| AUTO
+-----------------------+
|1UO|OOO:AAA|32B|XXX:100| INDEXED
+-----------------------+
|0UO|OOO:AAA|###|###:###| BYTE #/NOP
+-----------------------+
ST OP
0 NEG REG B=0
0 CTL SCC B=1
1 SWP SFT 0..7
2 JSR JCC+ B is branch flag
3 JSR JCC
4 R+ R+
5 X+# X+#
6 R+ R+
7 X+# X+#
40 NOP/QUICK
50 CTL/SCC
*/
// PROPERTY Atmel {pin_keep = off };
PROPERTY Atmel {soft_buffer = on};
// QUICK
NAME CTL.PLD ;
PARTNO ;
DATE 2025-04-29 ;
REVISION ;
DESIGNER ;
COMPANY ;
ASSEMBLY ;
LOCATION ;
DEVICE F1508PLCC84 ;
PINNODE = [OP4..1,PSW,SYNC,BUSY,BOUNCE,RS,PAN1,PAN2,OK,GO];
PINNODE = [LCTR,CC,CF,WCY,SFT,SF,ZF,TS,BRA,WF2,WF1];
PINNODE = [SX,LD,TWO,WRD,OP,RA,RX,BYY];
PINNODE = [Y,AUX,EF,ZLD,RK,TP,EFC,TSW,BY,WR,RD];
PINNODE = [CTR3..1,CTL,TST,STOP,IQ,IRQ,NO,TRAP,DSP,ODD];
PINNODE = [IR18..2,TIR,TIN,TMAR,PCL];
PIN 2 = ACK; // PHASE 2 CLOCK (AP IN)
PIN 4 = K1; // DATA MULX
PIN 5 = K2; // DATA MULX
PIN 70 = K3; // DATA MULX
/*
000 ZERO IN
001 BYTE IN
010 SEX IN BITS 3..1 SIGNED NUMBER
011 TWO IN
101 WORD IN
*/
PIN 8 = CP; // PHASE 1 CLOCK OUT
PIN 9 = SHO; // SHIFT OUT -L
PIN 25 = IRQI; // IRQ IN ACTIVE HIGH FROM 74LS14
PIN 1 = CLR; // RESET ACTIVE HIGH FROM 74LS14
PIN 11 = SH1; // RAM REG 00 LOAD 01 LOAD UNSIGNED
PIN 12 = SH2; // 1X SHIFT
// PIN 10 = JAM; // RESERVED
PIN 63 = C18; // CARRY FROM ALU
PIN 6 = APP; // ADDRESS CLOCK
PIN 67 = ALU3; // ALU FUNC
PIN 65 = ALU2; // ALU FUNC
PIN 64 = ALU1; // ALU FUNC
/*
00- ADD 01- SUB
100 AND 101 OR
110 XOR 111 LOAD
*/
PIN 27 = SWR1; // BOT ALD -L
PIN 28 = SWR2; // BOT+1 EXAM -L
PIN 29 = SWR3; // TOP-1 DEP -L
PIN 30 = SWR4; // TOP R/S -L
PIN 31 = SWR5; // PC/AC
// UN A SIGNED NODES
PIN = AD0; // AD7..AD0 MICRO CODE ROM ADDRESS
PIN = AD1;
PIN = AD2;
PIN = AD3;
PIN = AD4;
PIN = AD5;
PIN = AD6;
PIN = AD7;
PIN = RUN; // TRUE IF RUNING FALSE FRONT PANEL MODE
PIN = IR; // TRUE IF INSTRUCTION FETCH
PIN 22 = BI3; // DATA BUS INPUT 18..2 ACTIVE LOW
PIN 21 = BI2;
PIN 33 = BI18;
PIN 34 = BI17;
PIN 35 = BI16;
PIN 36 = BI15;
PIN 37 = BI14;
PIN 39 = BI13;
PIN 40 = BI12;
PIN 41 = BI11;
PIN 44 = BI10;
PIN 45 = BI9;
PIN 46 = BI8;
PIN 48 = BI7;
PIN 49 = BI6;
PIN 50 = BI5;
PIN 51 = BI4;
PIN 57 = YY; // Y MULX FOR MAR,JAM 0 SUM 1 RAM REG
PIN 54 = MR; // MEMORY REQUEST
PIN 55 = MW; // MEM WRITE
PIN 56 = MB; // MEM BYTE
PIN 52 = DK; // DCLOCK ACTIVE HIGH READ PANEL SWITCH
// DISPLAY MAR
PIN 60 = MAR; // LOAD MAR REG AND WR,BY FLAGS
PIN 61 = IN; // LOAD INPUT
PIN 71 = CY0; // CARRY OUT
PIN 79 = WE_; // 219 WRITE STROBE
PIN 68 = NSGN; // SIGN BIT RAM -L
PIN 73 = BOUT; // DATA BUS OUTPUT ENABLE WR&MR
PIN 74 = RG3; // 219 RAM AD 3
PIN 75 = RG2; // 219 RAM AD 2
PIN 76 = RG1; // 219 RAM AD 1
PIN 77 = RG4; // 219 RAM AD 4
PIN 58 = EQ; // EQ FLAG IN
PIN 69 = NODD; // ODD BIT FROM RAM -L
PIN 81 = CI; // 2X CLOCK
PIN 83 = CLK; // PHASE 1 CLOCK (CP IN )
PIN 84 = NF; // SIGN FLAG FROM SUM
/*
MICRO CODE STUFF
ROM A OUTPUTS
SH,NO,LD,RA,TWO,WRD,OP,WR
"SX", 0X0000C 3 bit data sign extended
"WRD",0X00004 word data
"2" ,0X00008 constant 2
"OP", 0X00002 alu opcode
"SUB",0X00002 subtract
"WR", 0X00001 WR/rd bus flag
"AC" ,0X00010 select ac
"LD" ,0X00020 load operation
"NO" ,0X00040 no load ram
BY,RX,XIR,IN,RD,MAR,Y,AUX
"BY", 0X08000 BY/wrd bus flag
"Y", 0X00200 select sum/ram to mar
"IR", 0X03000 fetch
"IN" ,0X01000 input data
"CTL",0X00100 control state AUX !RA !RX decode
"TST",0X00100 test acc and jump if true to 4 AUX AX
"DSP",0X00100 display mar and read swr AUX RX
BRA branch data AUX UNSIGNED
"SFT",0X00100 shift a input
"PC" ,0X00000 pc select
"MAR",0X00400 load mar
"IX" ,0X04000 rx index reg select
"RD", 0X00800 memory request
"SWR",0X04010 ac/pc switch display
*/
IR = TIR; // intruction fetch
IN = TIN; // load b input reg
MAR = TMAR; // load mar register
// alu operation
ST = !IR15&!IR14&!IR13;
OP4 = IR16;
OP3 = IR15;
OP2 = IR14;
OP1 = IR13;
CPE = OP&!OP3&OP2&OP1;
// front panel switches and irq
PSW.D = SWR5;
PSW.CK = CLK;
SYNC.D = (!SWR1#!SWR2#!SWR3#!SWR4)&!CLR;
SYNC.CK = CLK;
SYNC.CE = IR;
SYNC.AR = CLR;
BUSY.D = SYNC&!CLR;
BUSY.CK = CLK;
BUSY.CE = IR;
BUSY.AR = CLR;
BOUNCE.D = BUSY;
BOUNCE.CK = CLK;
BOUNCE.CE = IR;
BOUNCE.AR = CLR;
OK = SYNC&BUSY&!BOUNCE;
RS.D = !SWR4&OK;
RS.CK = CLK;
RS.CE = IR;
RS.AR = CLR;
PAN1.D = OK&(!SWR1#!SWR3)&!RUN;
PAN1.CK = CLK;
PAN1.CE = IR;
PAN1.AR = CLR;
PAN2.D = OK&(!SWR2#!SWR3)&!RUN;
PAN2.CK = CLK;
PAN2.CE = IR;
PAN2.AR = CLR;
// false panel true running
RUN.D = RUN & !STOP
#!RUN & RS;
RUN.CK = CLK;
RUN.CE = IR;
RUN.AR = CLR;
// INTERNAL TIMING AND FLIP FLOPS
// RAM STROBE
WE_.D = !(!NO&!CPE&CP&APP);
WE_.CK = CI;
// INTERNAL CLOCK GEN 4 PHASE
// START HIGH
CP.CK = CI;
CP.AP = CLR;
CP.D = !APP;
// SET HIGH ON CLEAR
APP.CK = CI;
APP.AR = CLR;
APP.D = CP&!CLR;
// FRONT PANEL DK
DK = DSP;
TP = EF & !CTL & IQ & RUN & IR ;
BRA = AUX & BYY;
/* MAIN IRQ ENABLE */
EF.D = CTL & IR4 // nop nop di ei nop nop hlt-di
#!CTL & RUN & EF & !TP;
EF.CK = CLK;
EF.CE = IR;
EF.AR = CLR;
IRQ.D = IRQI & RUN & !CTL ;
IRQ.CK = CLK;
IRQ.CE = IR;
IRQ.AR = CLR;
IQ.D = IRQ & RUN & !CTL;
IQ.CK = CLK;
IQ.CE = IR;
IQ.AR = CLR;
// SELECT ALU REGISTER
RG1 = RA&!RX & IR10 & RUN
# !RA& RX & IR4;
RG2 = RA&!RX & IR11 & RUN
# !RA& RX & IR5;
RG3 = RA&!RX & IR12 & RUN
# !RA& RX & IR6
# !RA&!RX // PC
# RA&RX&PSW; // PC,AC
PCL = !(IR6&!IR5&!IR4&!IR3);
// SELECT PC
RG4 = !RA&!RX // PC
# RA&RX&PSW // PC,AC
# !RA&RX&!(PCL#NO#IN); // IX IS PC
//
ZLD = !RA&RX &!IR6 & !IR5 & !IR4 & NO &!IN;
CTL = AUX & !RA & !RX & NO;
TST = AUX & RA;
DSP.D = AUX & RX;
DSP.CK = ACK;
DSP.AR = CLR;
BOUT.D = MW&!BOUT;
BOUT.CK = ACK;
BOUT.AR = CLR;
// MEMORY CONTROL
// GATE BUS BYTE REQUEST
MB.D = BY&BYY;
MB.CK = CLK;
MB.AR = CLR;
// WR/rd BUS REQUEST
MW.D = WR;
MW.CK = CLK;
MW.AR = CLR;
// MEMORY REQ STROBE
MR.D = RD;
MR.CK = ACK;
MR.AR = CLR;
STOP = CTL&IR6
# RUN&RS
# RUN&!SWR1&SYNC;
LCTR = TST &(CC$OP4); // NORMAL TESTS
YY = !RX & Y // SELECT RAM FOR OUTPUT PC++,AC++
# RX & Y & !IR3; // RAM FOR OUTPUT R++
CY0 = OP4 & OP & !OP3 & OP2 & CF
# !OP4 & OP & !OP3 & OP2 // SUB OPS
# OP & !OP3 &!OP2 &!OP1 &!OP4
# OP & !OP3 &!OP2 &!OP1 &OP4 & CF;// SUBTRACT
WCY = OP & !OP3 & (OP2#OP1) & !IR12 // ABCD ONLY
# OP & !OP3 & !OP2 & !OP1&!IR12 & IR; // NEG
BYY = RUN&(!IR18#IR7);
//HLT = RUN&!IR18&ST&!CTR2&!CTR3&IR6;
//K2 = TWO&!HLT;
K1 = WRD;
K2 = TWO;
K3 = WRD&!TWO&!(BYY&OP);
// WORD K1' SGN IN K2'
ALU1 = LD # ZLD
# OP &OP1;
ALU2 = LD&!BRA # ZLD
# OP & !OP3 &!OP2 &!OP1 // SUBTRACT
# OP & OP2 ;
ALU3 = LD&!BRA #ZLD
# OP&OP3;
SH1 = SFT & OP3 // DOWN SHIFT RIGHT
# IR17&OP&BYY; // UNSIGNED BYTE
// SHIFT 0..7
SH2 = SFT ;
INC = SFT & !(IR6&IR5&IR4);
SHO = OP2&OP1&NSGN // SHIFT OUT SIGN
# OP2&!OP1&CF;
TS.D = NSGN;
TS.CK = ACK;
// TEMP SIGN FLAG RAM 18
ODD.D = NODD;
ODD.CK = ACK;
//
WF1 = RA & IR & !IR12 // ALU OP
# SFT & !OP4 // SHIFT ANY REG
# SFT & OP4 & OP3;// OP FLAGS DOWN
// MOST OTHER AC OPS
// SWAP LEAVES FLAGS UNDEFINED
WF2 = SFT & OP4 ; // OP FLAGS
// 0 HOLD, 1 FLAGS, 2 FLAGS DOWN, FLAGS UP
CF.D = SFT&TS&!OP3 // SHIFT UP, CF = SIGN
# SFT&ODD&OP3&!OP4 // SHIFT DOWN, CF = ODD
# SFT&ZF&OP3&OP4 // SHIFT DOWN, CF = ZF FLAGS
#!SFT&!WCY&CF
#!SFT&WCY&C18;
CF.CK = CLK;
CC = (
// REGULAR CC
OP1&ZF&IR17
# OP2&SF&IR17
# OP1&EQ&!IR17
# OP2&TS&!IR17
# OP3&!CF
# OP3&OP2
);
// 0 HOLD
// 1 SET
// 2 UP SF <- ZF <- CF <- RAM18
// 3 DOWN CF -> SF -> ZF -> CF
SF.D = NF & WF1 & !WF2 // SUM18
# SF & !WF1 & !WF2
# ZF & !WF1 & WF2
# CF & WF1 & WF2;
// ALU SIGN
ZF.D = EQ & WF1 & !WF2 & !OP4 // NORMAL
# EQ & WF1 & !WF2 & OP4 & ZF // OP WITH CARRY - LONG
# ZF & !WF1 & !WF2
# CF & !WF1 & WF2 // UP
# SF & WF1 & WF2; // DOWN
// ALU ZERO FLAG
SF.CK = CLK;
ZF.CK = CLK;
$REPEAT N = [2,3,7..18]
IR{N}.CK = CLK;
IR{N}.CE = IR;
$REPEND
IR4.CK = CLK;
IR5.CK = CLK;
IR6.CK = CLK;
IR4.CE = IR # INC;
IR5.CE = IR # INC;
IR6.CE = IR # INC;
IR4.D = !BI4& !INC # !IR4&INC;
IR5.D = !BI5& !INC # (IR5$IR4)&INC;
IR6.D = !BI6& !INC # (IR6$(IR5&IR4))&INC;
$REPEAT N = [2,3,7..12]
IR{N}.D = !BI{N};
$REPEND
$REPEAT N = [13..18]
IR{N}.D = !BI{N}&!TP;
$REPEND
$REPEAT N = [3..1]
CTR{N}.CK = CLK;
CTR{N}.AR = CLR;
AD{N-1} = CT{N};
$REPEND
// 0..3 NORMAL PANEL
// 4..7 START PANEL
CT1 = CTR1;
CT2 = CTR2;
CT3 = CTR3;
CTR1.D = !LCTR & !IR & !CT1 & !INC
# CT1 & INC;
CTR2.D = !LCTR & !IR & (CT2$CT1) &!INC
# CT2 & INC
# TP;
CTR3.D = !IR & (CT3$(CT1&CT2))
# LCTR;
AD3 = !RUN & PAN1
# RUN & IR3&!IR2&IR18
# RUN & IR18&!IR9&!IR8&IR7; // SCC
AD4 = !RUN & PAN2
# RUN & IR8& IR18;
AD5 = RUN & IR9
# RUN & !IR18
# RUN & IR18&!IR9&!IR8&IR7; // SCC
AD6 = !IR15&!IR14&!IR13;
// STORE
AD7 = !RUN
# !IR18
#RUN&IR18&!IR9&!IR8&IR7; // SCC
@
/ START OF MICRO CODE
#000 / REG% REGISTER OP'S
PC MAR WR / OUTPUT IX FOR WRITE
IX WR IN / READ IN
PC 2 Y MAR
AC OP WRD IR RD
#010 / SHIFT 0..7
/ SHIFT 1..8 TIMES
/ IR6..4 IS INCRIMENTED N-1 TIMES
AC MAR / LOAD A
AC SFT / SHIFT A
PC 2 Y MAR
PC IR RD
#020 / JCC
IX SX Y MAR
AC TST RD IN
PC 2 Y MAR
AC IR RD
#024 / MET CC
SWR MAR
DSP
PC LD WRD AUX MAR
PC 2 IR RD
#030 / JMP INDEXED
PC 2 Y MAR
AC IN
IX NO WRD MAR
AC RD IN
PC LD WRD MAR
PC 2 IR RD
#040 / R+
IX SX Y MAR BY
AC RD IN BY
PC 2 Y MAR
AC WRD OP IR RD
#050 / MEM X
PC 2 Y MAR
AC RD IN
IX NO WRD MAR BY
AC RD IN BY
PC 2 Y MAR
AC OP WRD IR RD
#060 / R+
IX SX Y MAR
AC RD IN
PC NO LD WRD MAR BY
AC RD IN BY
PC 2 Y MAR
AC OP WRD IR RD
#070 / NOP
PC 2 Y MAR
AC RD IN
IX NO WRD MAR
AC RD IN
PC NO LD WRD MAR BY
AC RD IN BY
PC 2 Y MAR
AC OP WRD IR RD
/ STORE OPS
#100 / NEG
PC MAR WR / OUPUT IX FOR WRITE
AC LD WR IN / READ IN , CLEAR IX
PC 2 Y MAR
AC OP WRD IR RD / AC = 0 - AC
#110 / SWP
IX MAR
AC RD IN
IX WR
AC RD WR
PC 2 Y MAR
AC LD WRD IR RD
#120 / JSR -S X+
IX SX Y MAR
AC RD IN
AC 2 SUB MAR WR
PC RD WR
PC LD WRD AUX MAR
PC 2 IR RD
#130 /JSR INDEXED
PC 2 Y MAR
AC RD IN
IX NO WRD MAR
AC RD IN
AC 2 SUB MAR WR
PC RD WR
PC LD WRD MAR
PC 2 IR RD
#140 / ST R+
IX SX Y MAR WR BY
AC RD WR BY
PC 2 Y MAR
AC IR RD
#150 / MEM X
PC 2 Y MAR
AC RD IN
IX NO WRD MAR WR BY
AC RD WR BY
PC 2 Y MAR
AC IR RD
#160 / ST R+
IX SX Y MAR
AC RD IN
PC NO LD WRD MAR WR BY
AC RD WR BY
PC 2 Y MAR
AC IR RD
#170 / MEM X
PC 2 Y MAR
AC RD IN
IX NO WRD MAR
AC RD
PC LD NO WRD MAR WR BY
AC RD WR BY
PC 2 Y MAR
AC IR RD
/ EXTENDED OPS
#240 /QUICK
PC 2 Y MAR
AC OP WRD IR RD
#250 / SCC
AC TST MAR
PC 2 Y MAR
AC LD IR RD
#254 / MET CC
PC 2 Y MAR
AC LD SX IR RD
#340 / NOP
PC 2 Y MAR
IR RD
/ TRAP
/ PC->0 PC=2
PC SUB 2
PC LD NO MAR WR
PC RD WR
PC 2 LD MAR
PC 2 RD IR
#350 / CTL
PC 2 Y MAR
CTL NO IR RD
// PANEL OPS
#200 / IDLE
SWR MAR
DSP IN // DATA IN HERE
AC
PC IR IN // TOGGLE IN OFF
#210 / LOAD ADR
PC LD WRD
AC LD WRD
PC
PC IR
#220 / READ MEM -> AC
PC 2 Y MAR
AC RD IN
AC LD WRD
AC IR
#230 / WRITE MEM -> AC
AC WRD LD
PC 2 Y MAR WR
AC RD WR
PC IR
#300 / IDLE
SWR MAR
DSP IN // DATA IN HERE
AC
PC IR IN // TOGGLE IN OFF
#310 / LOAD ADR
PC LD WRD
AC LD WRD
PC
PC IR
#320 / READ MEM -> AC
PC 2 Y MAR
AC RD IN
AC LD WRD
AC IR
#330 / WRITE MEM -> AC
AC WRD LD
PC 2 Y MAR WR
AC RD WR
PC IR
@
/*
S A S G A V A C C G R W V R R R
H D H C N P K K C C LN L N C U E C G G G
1 1 O P D P 2 1 C K RF K D I N _ C 4 1 2
-------------------------------------------
/ 11 9 7 5 3 1 83 81 79 77 75 \
/ 10 8 6 4 2 84 82 80 78 76 \
SH2 | 12 (*) 74 | RG3
VCC | 13 73 | BOUT
AD7 | 14 72 | GND
AD2 | 15 71 | CY0
AD3 | 16 70 | K3
AD5 | 17 69 | NODD
AD0 | 18 68 | NSGN
GND | 19 67 | ALU3
| 20 66 | VCC
BI2 | 21 65 | ALU2
BI3 | 22 ATF1508 64 | ALU1
AD4 | 23 84-Lead PLCC 63 | C18
AD6 | 24 62 | IR
IRQI | 25 61 | IN
VCC | 26 60 | MAR
SWR1 | 27 59 | GND
SWR2 | 28 58 | EQ
SWR3 | 29 57 | YY
SWR4 | 30 56 | MB
SWR5 | 31 55 | MW
GND | 32 54 | MR
\ 34 36 38 40 42 44 46 48 50 52 /
\ 33 35 37 39 41 43 45 47 49 51 53/
--------------------------------------------
B B B B B V B B B G V B B B G B B B B D V
I I I I I C I I I N C I I I N I I I I K C
1 1 1 1 1 C 1 1 1 D C 1 9 8 D 7 6 5 4 C
8 7 6 5 4 3 2 1 0
*/
@
/ ALL DONE
High 1508 Code: // APRIL 28 2025
// 74F218 RAM SH1 UNSIGNED BYTES NO JAM
// PROPERTY Atmel {pin_keep=off};
PROPERTY Atmel {soft_buffer = on};
// QUICK
NAME KAH;
PARTNO CPLD;
REVISION 01;
DATE april 28 2025;
DESIGNER ;
COMPANY ;
LOCATION NONE;
ASSEMBLY NONE;
DEVICE F1508PLCC84;
/* ACTIVE LOW BUS */
PINNODE = [FADD,FXOR,FAND,NTB,TFR];
PINNODE = [TI9..0,TM9..1,GP9..1];
PINNODE = [PP9..1,DI9..1,CC1..8];
PINNODE = [REG1..9,PRO];
PIN 2 = ACK;
PIN 4 = RG4;
PIN 5 = RG5;
PIN 6 = RG6;
PIN 8 = SUM7;
PIN 9 = SUM8;
PIN 10 = SUM9;
PIN 11 = RG7;
PIN 12 = RG8;
PIN 14 = RG9;
PIN 15 = RG10;
PIN 70 = RG0;
PIN 17 = CC9;
PIN 30 = EQ;
PIN 20 = ALU3;
PIN 21 = ALU2;
PIN 22 = ALU1;
PIN 18 = K3;
PIN 69 = CC0;
PIN 27 = LMAR;
PIN 28 = SH2;
PIN 29 = SH1;
PIN 25 = LDI;
//PIN 1 = JAM;
PIN 31 = Y;
PIN 33 = BI9;
PIN 34 = MAR9;
PIN 35 = BI8;
PIN 36 = MAR8;
PIN 37 = BI7;
PIN 39 = MAR7;
PIN 40 = BI6;
PIN 41 = MAR6;
PIN 44 = BI5;
PIN 45 = MAR5;
PIN 46 = BI4;
PIN 48 = MAR4;
PIN 49 = BI3;
PIN 50 = MAR3;
PIN 51 = BI2;
PIN 52 = MAR2;
PIN 54 = BI1;
PIN 55 = MAR1;
PIN 62 = SX;
PIN 68 = EQI;
PIN 71 = SUM1;
PIN 73 = SUM2;
PIN 74 = SUM3;
PIN 75 = RG1;
PIN 76 = RG2;
PIN 77 = RG3;
PIN 79 = SUM4;
PIN 80 = SUM5;
PIN 81 = SUM6;
PIN 83 = CLK;
PIN 84 = BOUT;
TFR = ALU3&ALU2&ALU1;
FADD = !ALU3;
FAND = ALU3&!ALU2;
FXOR = !(ALU3&!ALU2&!ALU1);
NTB = !ALU3&ALU2;
/* ACTIVE LOW INPUT */
$REPEAT N = [1..9]
REG{N}.D = RG{N}&!SH2 // NORMAL RAM
# (RG{N-1})& SH2&!SH1 // SHIFT UP LEFT
# (RG{N+1})& SH2& SH1; // SHIFT DOWN RIGHT
REG{N}.CK = ACK;
MAR{N}.D = Y®{N}#!Y&SUM{N};
MAR{N}.CK = CLK;
MAR{N}.CE = LMAR;
// INPUT REG BUS,SUM,MAR
TI{N}.D = !BI{N}.IO;
TI{N}.CK = CLK;
TI{N}.CE = LDI;
BI{N} = !REG{N};
BI{N}.OE = BOUT;
$REPEND
/* ADDER */
/* 00 ADD 01 XOR 10 AND 11 OR */
$REPEAT N = [1..9]
PP{N} = (REG{N}$DI{N})&FXOR
# (GP{N})& FAND;
GP{N} = REG{N}&DI{N};
SUM{N} = (((CC{N-1}&FADD)$PP{N})&!TFR
# DI{N}&TFR);
$REPEND
$REPEAT N = [1..9]
DI{N} = ((TI{N} & K3# SX & !K3 & !SH1)$NTB) ;
$REPEND
$REPEAT N = [1,4,7]
CC{N} = CC{N-1} & PP{N} # GP{N};
CC{N+1} = (CC{N-1} & PP{N} # GP{N})&PP{N+1}#GP{N+1};
CC{N+2} = ((CC{N-1} & PP{N} # GP{N})&PP{N+1}#GP{N+1})&PP{N+2}#GP{N+2};
$REPEND
EQ = !SUM1&!SUM2&!SUM3&!SUM4&!SUM5&!SUM6&!SUM7&!SUM8&!SUM9&EQI;
/*
S S S B S S S
R U U U G R R R V A O C G U U U V R R R
G M M M N G G G C C U L N M M M C G G G
7 9 8 7 D 6 5 4 C K T K D 6 5 4 C 3 2 1
-------------------------------------------
/ 11 9 7 5 3 1 83 81 79 77 75 \
/ 10 8 6 4 2 84 82 80 78 76 \
RG8 | 12 (*) 74 | SUM3
VCC | 13 73 | SUM2
RG9 | 14 72 | GND
RG10 | 15 71 | SUM1
| 16 70 | RG0
CC9 | 17 69 | CC0
K3 | 18 68 | EQI
GND | 19 67 |
ALU3 | 20 66 | VCC
ALU2 | 21 65 |
ALU1 | 22 ATF1508 64 |
| 23 84-Lead PLCC 63 |
| 24 62 | SX
LDI | 25 61 |
VCC | 26 60 |
LMAR | 27 59 | GND
SH2 | 28 58 |
SH1 | 29 57 |
EQ | 30 56 |
Y | 31 55 | MAR1
GND | 32 54 | BI1
\ 34 36 38 40 42 44 46 48 50 52 /
\ 33 35 37 39 41 43 45 47 49 51 53/
--------------------------------------------
B M B M B V M B M G V B M B G M B M B M V
I A I A I C A I A N C I A I N A I A I A C
9 R 8 R 7 C R 6 R D C 5 R 4 D R 3 R 2 R C
9 8 7 6 5 4 3 2
*/
LOW 1508 Code: // LOW CPLD APRIL 28,2024
// 74F218 74181 encoding
// PROPERTY Atmel {pin_keep = off };
PROPERTY Atmel {soft_buffer = on};
// QUICK
NAME KAL;
PARTNO CPLD;
REVISION 01;
DATE APRIL 28 2025;
DESIGNER ;
COMPANY ;
LOCATION NONE;
ASSEMBLY NONE;
DEVICE F1508PLCC84;
/* ACTIVE LOW BUS */
PINNODE = [FADD,FXOR,FAND,NTB,TFR,PAS,KK];
PINNODE = [TI9..1,TM9..1,GP9..1];
PINNODE = [PP9..1,DI9..1,CC1..8];
PINNODE = [REG1..9];
PIN 58 = BUF; // CLOCK BUFFER 2 gate delays
PIN 2 = ACK;
PIN 4 = RG4;
PIN 5 = RG5;
PIN 6 = RG6;
PIN 8 = SUM7;
PIN 9 = SUM8;
PIN 10 = SUM9;
PIN 11 = RG7;
PIN 12 = RG8;
PIN 14 = RG9;
PIN 15 = RG10;
PIN 16 = RG0;
PIN 17 = CC9;
PIN 18 = EQ;
PIN 20 = ALU3;
PIN 21 = ALU2;
PIN 22 = ALU1;
PIN 23 = SX;
PIN 24 = CC0;
PIN 27 = LMAR;
PIN 28 = SH2;
PIN 29 = SH1;
PIN 25 = LDI;
//PIN 1 = JAM;
PIN 30 = Y;
PIN 31 = CCLK;
PIN 33 = BI9;
PIN 34 = MAR9;
PIN 35 = BI8;
PIN 36 = MAR8;
PIN 37 = BI7;
PIN 39 = MAR7;
PIN 40 = BI6;
PIN 41 = MAR6;
PIN 44 = BI5;
PIN 45 = MAR5;
PIN 46 = BI4;
PIN 48 = MAR4;
PIN 49 = BI3;
PIN 50 = MAR3;
PIN 51 = BI2;
PIN 52 = MAR2;
PIN 54 = BI1;
PIN 55 = MAR1;
PIN 71 = SUM1;
PIN 73 = SUM2;
PIN 74 = SUM3;
PIN 75 = RG1;
PIN 76 = RG2;
PIN 77 = RG3;
PIN 79 = SUM4;
PIN 80 = SUM5;
PIN 81 = SUM6;
PIN 83 = CLK;
PIN 84 = BOUT;
PIN [69,70] = [K2,K1];
TFR = ALU3&ALU2&ALU1;
FADD = !ALU3;
FAND = ALU3&!ALU2;
FXOR = !(ALU3&!ALU2&!ALU1);
NTB = !ALU3&ALU2;
/* ACTIVE LOW INPUT */
$REPEAT N = [1..9]
REG{N}.D = RG{N}&!SH2 // NORMAL RAM
# (RG{N-1})& SH2&!SH1 // SHIFT UP LEFT
# (RG{N+1})& SH2& SH1; // SHIFT DOWN RIGHT
REG{N}.CK = ACK;
MAR{N}.D = Y®{N}#!Y&SUM{N};
MAR{N}.CK = CLK;
MAR{N}.CE = LMAR;
// INPUT REG BUS,SUM,MAR
TI{N}.D = !BI{N}.IO;
TI{N}.CK = CLK;
TI{N}.CE = LDI;
BI{N} = !REG{N};
BI{N}.OE = BOUT;
$REPEND
/* ADDER */
/* 00 ADD 01 XOR 10 AND 11 OR */
$REPEAT N = [1..9]
PP{N} = (REG{N}$DI{N})&FXOR
# (GP{N})& FAND;
GP{N} = REG{N}&DI{N};
SUM{N} = (((CC{N-1}&FADD)$PP{N})&!TFR
# DI{N}&TFR);
$REPEND
// LOW
// K1 !K2 PASS WORD
// K1 K2 PASS SX (3 bits)
// !K1 !K2 0
// !K1 K2 2
PAS = K1&!K2; // WORD PASS
DI1 = ((K1& TI1)$NTB); // PASS INPUT
DI2 = ((!K1 & K2 // CONSTANT 0 or 2
# K1& TI2)$NTB); // PASS INPUT
DI3 = ((K1& TI3)$NTB); // PASS INPUT
KK = K1 & TI3; // SIGN EXTEND
$REPEAT N = [4..9]
DI{N} = ((TI{N} & PAS # KK &!PAS)$NTB);
$REPEND
$REPEAT N = [1,4,7]
CC{N} = CC{N-1} & PP{N} # GP{N};
CC{N+1} = (CC{N-1} & PP{N} # GP{N})&PP{N+1}#GP{N+1};
CC{N+2} = ((CC{N-1} & PP{N} # GP{N})&PP{N+1}#GP{N+1})&PP{N+2}#GP{N+2};
$REPEND
EQ = !SUM1&!SUM2&!SUM3&!SUM4&!SUM5&!SUM6&!SUM7&!SUM8&!SUM9;
SX = TI9 & PAS # KK &!PAS; // BIT #9 OR BIT #3
BUF = !CLK; // DELAY x 1
CCLK = !BUF.IO; // BUFFERED CLOCK OUT DELAY X 2
/*
S S S B S S S
R U U U G R R R V A O C G U U U V R R R
G M M M N G G G C C U L N M M M C G G G
7 9 8 7 D 6 5 4 C K T K D 6 5 4 C 3 2 1
-------------------------------------------
/ 11 9 7 5 3 1 83 81 79 77 75 \
/ 10 8 6 4 2 84 82 80 78 76 \
RG8 | 12 (*) 74 | SUM3
VCC | 13 73 | SUM2
RG9 | 14 72 | GND
RG10 | 15 71 | SUM1
RG0 | 16 70 | K1
CC9 | 17 69 | K2
EQ | 18 68 |
GND | 19 67 |
ALU3 | 20 66 | VCC
ALU2 | 21 65 |
ALU1 | 22 ATF1508 64 |
SX | 23 84-Lead PLCC 63 |
CC0 | 24 62 |
LDI | 25 61 |
VCC | 26 60 |
LMAR | 27 59 | GND
SH2 | 28 58 | BUF
SH1 | 29 57 |
Y | 30 56 |
CCLK | 31 55 | MAR1
GND | 32 54 | BI1
\ 34 36 38 40 42 44 46 48 50 52 /
\ 33 35 37 39 41 43 45 47 49 51 53/
--------------------------------------------
B M B M B V M B M G V B M B G M B M B M V
I A I A I C A I A N C I A I N A I A I A C
9 R 8 R 7 C R 6 R D C 5 R 4 D R 3 R 2 R C
9 8 7 6 5 4 3 2
*/
schematic Ben. PS i have few spare PCB's around, it you want to build one.
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