Sometimes I am not sure I should post.

I can empathize with Ben’s feeling about the excrement. I think it is in part due to the pace of development. Just when you think you have something figured out, it is new again. Compatibility issues galore. I predict it wont be quite as bad in the future once things are more mature and stabilized. Some people used to composite still think of VGA as new when things have moved on. I had a great realization about 20+ years ago that medium scale logic was on the way out, with all the highly integrated chips coming out and PLD’s like FPGA’s. The environment was changing so fast that I could see it changing.

Low-cost FPGA’s do not have enough capacity to do what I want, which is to build a large network of superscalar cores. On the other hand, I am not willing to wait the length of time required for tools to build such a system. If the build time gets to being more than ½ hour I lose interest. So, I am happily working away on smaller stuff. Besides, I must get the small stuff working well first, before tackling larger things.

Or, they could be used to build something bigger. I have three of those networked ATM, I was going to try learning about MPI.

I have no Idea what superscalar cores are, but anything with more than one core
is now a design is sharing memory rather than cpu logic. Who uses all that memory
bandwidth in the system.No use haveing fast fast floating point, when your aps are
streaming you-tube videos.

Ben: Still designing CORE memory computers with my fpga.

I got my TL88II+ working. Had to play with finding the right USB, and for that I needed to find my only LONG
usb cable to fit from the rear of the computer. Ben.

Added BCD math to the cpu. I was planning to use a 82S82 Bcd alu (1973) but they can't be found any more.
I can use a 22v10 , 74LS283 adder , and 74ls08 and gates to replace the 82S82 and a multiplexer.
Most of the logic was taken from http://6502.org/users/dieter/index.htm and thank you Dieter for the information.
Spare logic with the PAL can get me BCD shift right,left by 2 correction.
Tomorow will be testing the logic, and shifts. Soon I hope to write 8 digit BCD floating point routines.
Ben.

BCD was not working, checks the MC10800 schematic again.
2 22v10 are needed rather than a 82S100 do to limited pin out
out on the 22v10's. The logic is messy but simple to impliment.
Ben.

I hacked the 20 bit computer to use 12/24 bit data, with 20 bit opcodes.
The Front panel now sign extends bit 20 for the top most hex digit. This still
lets me load 20 bit programs from the front panel for debugging.
A 24 bit front panel is expected to be 12" wide rather than 10" for the 20 bit panel.

Hardware wise 2-12 bit alu cards will form the data path. 1x 120 pin 2.54 mm
card edge connector (from china) for the bus.

The computer was expanded to permit a 48 bit floating point number.
± 10 BCD digits and a ± 63 exponent. This lets me do $ 99.999.999.99
for a BASIC program when I get a floating point BASIC running.
For 1970's this seems a ample range for personal acounting,and floating point
in general compated with a 32 bit binary floating point.
Software wise not much change other a few constants in the code.

Floating point +-*/ is done, now I need to write I/O routines.
Ben.

Have you got photos Ben? It would be good to see this machine as it develops.

I recall working on routines to print a floating-point number. It is more complex than the float arithmetic. There’s a lot of shifting values back and forth to try and get reasonable looking output. If I recall correctly it was about 1000 LOC to display something. I should have a copy of the code somewhere written in assembler. Might be useful for reference.

That was the main reason I went BCD, I/O is really simple. I have Dubble Dabble and Revese Dubble
dabble correction for Dubble Dabble shifting.

Software floating point reqiures a lot of BCD shifting loops. A 22v10 pal will let do a 4 bit barrel shifter. Left , right 1..4 bits. The flag register can hold flags or a BCD digit. By using a table lookup I plan to pack
2 bcd digits into 7 bits. This will let me get a extra BCD digit for the 40 bit floating point.

Ben.

Thanks for the photos - very nice! A real lights and switches front panel...

and quite handy for debugging a 'off by one' with my barrel shifter logic. Ben.

You could try 35nS Everspin or Avalanche Parallel MRAM.
Not exactly core, as tunnel junction reads aren't destructive.

Also remind IBM 1620 CADET (Can't Add Doesn't Even Try)
stored BCD addition and multiplication cheat tables in core.

I have gone to the dark side. Fash Eproms and Excess 3


The latest version, is a 8/16/48 bit cpu. Odd Computer 4802.
(3 16 bit alu cards) .

I was using just 20v8 gals, but a 22v10 lets me put all my messy D input logic to the ALU into one chip.
This lets me have a 3 chips per each 4 bit slice, with a easy pcb layout. Ball park timing using 1984 PAL's
gets me to a 2 MHZ clock.
Excess 3 correction is the next cycle after normal binary operations.
A 16L8 handles 4 bits of carry look ahead, and forces a 0 as carry in for excess 3 adjustment.
Once done with the 4802, I can take a revised look at the 20 bit computer.
Ben.