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 WYSIWISC: What You See Is What It Should Compute 
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Alikberov
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Joined: Sat Feb 13, 2021 12:22 pm
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Location: https://en.wikipedia.org/wiki/Tashkent
Post WYSIWISC: What You See Is What It Should Compute
oldben wrote:
At the moment, I encountered a rather strange situation. :|

snip
BC B8 90 90 45 6E EOR B8,9#D4+5,C6 ???[/code]Lines with "???" indicate a new problem: We have double pointer - delegated and immediate.

Previously, the combo «MOV 9#D4+5,B8» could simply mean «LEA D9,[IP+2]» + «MOV [eval("D4+5")],D8H» (CISC: "redefine delegate" + "move").
But now, as I strive for very strict command decoding (less CISC-commands), I see this as a new problem.

Would a double pointer imply *(arg1 + scaled arg2 ...) ?
LEA is a needed instruction for most modern computing.

>P.S.: Anyway, in options "CISC vs RISC" I wish looking for RISC.


I am with unimpressed load/store architecture. I very unimpressed with the x86. I like the early machines as they had ample word
size for floating point 36+ bits, and a simple addressing modes ( often only 1).
Accessing external memory is slow, and think that the early designs had the best solution for that problem.

Hm...
With complex prefix we can have any vector with scales:
Code:
Prefixes         Vector                  Description
12               #D1+2                   "#D1" is base - not index in later!
   34            #D1+D3+24               [D1+(D3)+24]
      15         #D1+2D3+245             [D1+(2*(D3))+245] - "D1" is shifter
         67      #D1+2D3+D6+2457         [D1+(2*(D3)+D6)+2457]
            68   #D1+4D3+3D6+24578       [D1+(2*(2*(D3)+D6)+D6)+24578] - "D6" is repeated in nest!

Thus we can encode any vector:
Code:
12 23 24 65 27 89 10

is means vector
Code:
#D1+14D2+4D6+2D8+2345790 → [D1+14*D2+4*D6+2*D8+2345790]

  1. `12` → `#D1+2`
  2. `23` → `#D1+D2+23`
  3. `24` → `#D1+3D2+234` (`#D1+2D2+D2+234`)
  4. `65` → `#D1+3D2+D6+2345`
  5. `27` → `#D1+7D2+2D6+23457` (`#D1+6D2+4D6+D2+23457`)
  6. `89` → `#D1+7D2+2D6+D8+234579`
  7. `10` → `#D1+14D2+4D6+2D8+2345790`
My Verilog-model and i8080-parser can decode this prefixes.
Attachment:
i8080-wysiwisc-vector_decoder.png

Attachment:
WYSIWISC-DECODE_VECTOR.ASM.zip

You can run online:
  1. Just unpack binary
    Attachment:
    WISC-LEA.RKR.zip
  2. Press Image button
  3. Type codes «12 23 24 65 27 89 10 00» using numbers and space-bar, then press Enter
______________________________
Well. Lets recall basic principles for encoding ALU-commands in "strict mode".

In "flat-RISC" interpretation of byte-code we have few "trash commands":
Code:
Prohibited operation             Notice
MOV A0,A0                        MOV PSW,PSW - is nonsense
MOV A0,D                         MOV PSW-byte,D-word - is incompatable
MOV D,A0                         MOV D-word,PSW-byte - is incompatable
---
ADD A0,R                         ALU PSW,R - is forbidden
ADD R,A0                         ALU R,PSW - is forbidden


If we start clean up it cases with restrictions, we get "smart-CISC commands":
Code:
MOV A0,D                         INF PSW,D - try input (is port exist? CF="1" if it exist)
MOV D,A0                         INF D,PSW - try output (is port exist? CF="1" if it exist)
---
ADD A0,R                         INC CF,R - conditional increment (if CF="1")
ADD R,A0                         INC R - unconditional increment


As the "ADD PSW,PSW" is forbidden, with prefixes we have unary operations:
Code:
ADD A0,#D1+2,A0                  INC #D1+2
SUB A0,#D1+2,A0                  DEC #D1+2
AND A0,#D1+2,A0                  CLR #D1+2
OR  A0,#D1+2,A0                  SET #D1+2
EOR A0,#D1+2,A0                  NOT #D1+2

Linear assembler can encode it all (over 28 cases).
And Verilog-model can decode this (over 28 different instructions):
Code:
_IP_:M#[VV]IC  M_V_AD_E_AD_F RC<>TR _ASM ..OPERANDS..   _REAL INSTRUCTION_
0000:      AA  0_0_x0_x_0x_0:A?!=0?  CTX   A,A
0001:      A0  0_0_x0_x_00_0:A?!=AA  REG   A0
0002:03#   A0  1_0_10_0_00_0:@0!=AA  REG3  A0
0005:      0F  0_0_10_1_10_1:@0==@0  ---   ???          ; MOV   A0,A0
0006:      0E  0_0_10_1_10_0:@0==@0  ---   ???          ; EOR   A0,A0
0007:      0D  0_0_10_1_10_0:@0==@0  ---   ???          ; DIS   A0,A0
0008:      0C  0_0_10_1_10_0:@0==@0  ---   ???          ; CON   A0,A0
0009:      0B  0_0_10_1_10_0:@0==@0  ---   ???          ; SUB   A0,A0
000A:      0A  0_0_10_1_10_0:@0==@0  ---   ???          ; ADD   A0,A0
000B:   34 0F  0_1_10_1_10_1:@0==@0  MOV   PSW,D3+4     ; MOV   A0,D3+4,A0
000D:   34 0E  0_1_10_1_10_0:@0==@0  NOT   D3+4         ; EOR   A0,D3+4,A0
000F:      AD  0_0_10_0_00_0:@0!=AA  CTX   A,D
0010:      5F  0_0_10_0_01_1:@0!=#5  INF   D5           ; MOV   A0,D5
0011:      5E  0_0_10_0_01_0:@0!=#5  NOT   D5           ; EOR   A0,D5
0012:   34 5F  0_1_10_0_01_1:@0!=#5  SWP   D3+4,D5      ; MOV   A0,D3+4,D5
0014:   34 5E  0_1_10_0_01_0:@0!=#5  EOR   D3+4,D5      ; EOR   A0,D3+4,D5
0016:      AC  0_0_10_0_01_0:@0!=#a  CTX   A,C
0017:      5F  0_0_10_0_00_1:@0!=C5  MOV   PSW,C5       ; MOV   A0,C5
0018:      5E  0_0_10_0_00_0:@0!=C5  NOT   C5           ; EOR   A0,C5
0019:   34 5F  0_1_10_0_00_1:@0!=C5  SWP   D3+4,C5      ; MOV   A0,D3+4,C5
001B:   34 5E  0_1_10_0_00_0:@0!=C5  EOR   D3+4,C5      ; EOR   A0,D3+4,C5
001D:      DA  0_0_10_0_00_0:@0!=CD  CTX   D,A
001E:      D1  0_0_01_0_00_0:#x!=AD  REG   D1
001F:      0F  0_0_01_0_10_1:#1!=@0  OUF   D1           ; MOV   D1,A0
0020:      0E  0_0_01_0_10_0:#1!=@0  NOT   D1,CF        ; EOR   D1,A0
0021:   34 0F  0_1_01_0_10_1:#1!=@0  MOV   D1,D3+4      ; MOV   D1,D3+4,A0
0023:   34 0E  0_1_01_0_10_0:#1!=@0  EOR   D1,D3+4      ; EOR   D1,D3+4,A0
0025:      CA  0_0_01_0_00_0:#1!=AC  CTX   C,A
0026:      C2  0_0_00_0_00_0:C?!=AC  REG   C2
0027:      0F  0_0_00_0_10_1:C2!=@0  MOV   C2,PSW       ; MOV   C2,A0
0028:      0E  0_0_00_0_10_0:C2!=@0  NOT   C2,CF        ; EOR   C2,A0
0029:   34 0F  0_1_00_0_10_1:C2!=@0  MOV   C2,D3+4      ; MOV   C2,D3+4,A0
002B:   34 0E  0_1_00_0_10_0:C2!=@0  EOR   C2,D3+4      ; EOR   C2,D3+4,A0
002D:      DD  0_0_00_0_00_0:C2!=AD  CTX   D,D
002E:      1F  0_0_01_1_01_1:#1==#1  ???   D1           ; MOV   D1,D1
002F:      1E  0_0_01_1_01_0:#1==#1  NEG   D1           ; EOR   D1,D1
0030:      1D  0_0_01_1_01_0:#1==#1  STD   D1           ; DIS   D1,D1
0031:      1C  0_0_01_1_01_0:#1==#1  CLN   D1           ; CON   D1,D1
0032:      1B  0_0_01_1_01_0:#1==#1  SUB   D1           ; SUB   D1,D1
0033:      1A  0_0_01_1_01_0:#1==#1  ADD   D1           ; ADD   D1,D1
0034:06#34 5F  1_1_01_0_01_1:#1!=#5  ORD6  D1,D3+4,D5   ; MOV   D1,D3+4,D5
0038:   34 5E  0_1_01_0_01_0:#1!=#5  EOR   D1,D3+4,D5   ; EOR   D1,D3+4,D5
003A:   34 1F  0_1_01_1_01_1:#1==#1  LEA   D1,D3+4      ; MOV   D1,D3+4,D1
003C:   34 1E  0_1_01_1_01_0:#1==#1  RRC   D1,D3+4,D1   ; EOR   D1,D3+4,D1
003E:   34 1D  0_1_01_1_01_0:#1==#1  SAL   D1,D3+4,D1   ; DIS   D1,D3+4,D1
0040:   34 1C  0_1_01_1_01_0:#1==#1  SAR   D1,D3+4,D1   ; CON   D1,D3+4,D1
0042:   34 1B  0_1_01_1_01_0:#1==#1  SUB   D1,D3+4,D1   ; SUB   D1,D3+4,D1
0044:   34 1A  0_1_01_1_01_0:#1==#1  MUL   D1,D3+4,D1   ; ADD   D1,D3+4,D1
0046:      DB  0_0_01_0_01_0:#1!=#d  CTX   D,B
0047:      5F  0_0_01_0_00_1:#1!=B5  OUT   D1,B5        ; MOV   D1,B5
0048:      5E  0_0_01_0_00_0:#1!=B5  EOR   D1,B5        ; EOR   D1,B5
0049:   34 5F  0_1_01_0_00_1:#1!=B5  LEX   D1,D3+4,B5   ; MOV   D1,D3+4,B5
004B:   34 5E  0_1_01_0_00_0:#1!=B5  EOR   D1,D3+4,B5   ; EOR   D1,D3+4,B5
004D:      CD  0_0_01_0_00_0:#1!=BC  CTX   C,D
004E:      5F  0_0_00_0_01_1:C2!=#5  MOV   C2,D5        ; MOV   C2,D5
004F:      5E  0_0_00_0_01_0:C2!=#5  EOR   C2,D5        ; EOR   C2,D5
0050:   34 5F  0_1_00_0_01_1:C2!=#5  ???   C2,D3+4,D5   ; MOV   C2,D3+4,D5
0052:   34 5E  0_1_00_0_01_0:C2!=#5  EOR   C2,D3+4,D5   ; EOR   C2,D3+4,D5
0054:      CC  0_0_00_0_01_0:C2!=#c  CTX   C,C
0055:      2F  0_0_00_1_00_1:C2==C2  MOV   C2,C2        ; MOV   C2,C2
0056:      2E  0_0_00_1_00_0:C2==C2  NEG   C2,C2        ; EOR   C2,C2
0057:      2D  0_0_00_1_00_0:C2==C2  STD   C2,C2        ; DIS   C2,C2
0058:      2C  0_0_00_1_00_0:C2==C2  CLN   C2,C2        ; CON   C2,C2
0059:      2B  0_0_00_1_00_0:C2==C2  SUB   C2,C2        ; SUB   C2,C2
005A:      2A  0_0_00_1_00_0:C2==C2  ADD   C2,C2        ; ADD   C2,C2
005B:   34 2F  0_1_00_1_00_1:C2==C2  LEX   C2,D3+4,C2   ; MOV   C2,D3+4,C2
005D:   34 2E  0_1_00_1_00_0:C2==C2  RRC   C2,D3+4,C2   ; EOR   C2,D3+4,C2
005F:   34 2D  0_1_00_1_00_0:C2==C2  SAL   C2,D3+4,C2   ; DIS   C2,D3+4,C2
0061:   34 2C  0_1_00_1_00_0:C2==C2  SAR   C2,D3+4,C2   ; CON   C2,D3+4,C2
0063:   34 2B  0_1_00_1_00_0:C2==C2  SUB   C2,D3+4,C2   ; SUB   C2,D3+4,C2
0065:   34 2A  0_1_00_1_00_0:C2==C2  MUL   C2,D3+4,C2   ; ADD   C2,D3+4,C2
0067:   34 5F  0_1_00_0_00_1:C2!=C5  ORD   C2,D3+4,C5   ; MOV   C2,D3+4,C5
0069:   34 5E  0_1_00_0_00_0:C2!=C5  EOR   C2,D3+4,C5   ; EOR   C2,D3+4,C5
006B:      DB  0_0_00_0_00_0:C2!=CD  CTX   D,B
006C:      B7  0_0_01_0_00_1:#1!=BB  MOV   D1,B7
006D:      C7  0_0_01_0_00_1:#1!=BC  MOV   D1,C7
006E:      CF  0_0_01_0_00_1:#1!=BC  NOT   CF           ; CMC / Carry Flip
006F:      CE  0_0_01_0_00_0:#1!=BC  ERA   CF           ; CLC / Carry Erase
0070:   34 CF  0_1_01_0_00_1:#1!=BC  JCF   D3+4         ; JC    D3+4
0072:   34 CE  0_1_01_0_00_0:#1!=BC  JCE   D3+4         ; JNC   D3+4


Let me remind You that the goal is not to do something similar to CISC or RISC, but to end up with intuitively understandable code with context and subtext, where "strictness" simply eliminates ambiguity, but at the same time, as a side effect, provides convenient features.
As neural bot concludes in the end, such an approach is not just "a certain architecture", but "a whole philosophy"!

P.S.: Poetical speaking, I am "feeling out" not just a "computational stone", but already something like a "philosopher's stone of computation" :lol:


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Sun Mar 16, 2025 10:00 pm WWW
Alikberov
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Joined: Sat Feb 13, 2021 12:22 pm
Posts: 21
Location: https://en.wikipedia.org/wiki/Tashkent
Post WYSIWISC: What You See Is What It Should Compute
I looking back many times for complex prefixes mode and trying touch optimal path of conception developing.
  1. Like "Virtual Java Machine": I think about "Virtual WYSIWISC-Machine" for i8080, z80, i8086.
  2. With "clean bottom": I looking for "underwater stones" and try exclude many of lot.

Virtual WYSIWISC-Machine
Like Fortran, Pascal or C, concept of WYSIWISC is looking good as P-Code, if looking "deeply".
If Basic in regular dialects based on tokens model with no hardware realize, in case with WYSIWISC we haves:
  1. The chance for hardware TTL IC building (first model of 2019 - draft in Logisim)
  2. The chance Verilog-modeling for FPGA (I run my first prototype in Quartus before "my PC crashed & BSODed" in 2021)
  3. The chance for architecture scaling (from 30 APRs A0-A9/B0-B9/C0-C9 to billions - A1234567890 e.t.c.)

In current time I watching problem in combo «Delegate»+«Vector» over few instructions:
  • «Delegate»+«Vector»+«HLT» → «Redefine Delegate» - good solution
  • «Delegate»+«HLT» → «Debug Delegate» - good solution
  • «Delegate»+«ALU operation» → «ALU operation with delegated vector» - good solution
  • «Delegate»+«Vector»+«ALU operation» → strange combination - problem/!\
  • «Delegate»+«Vector»+«REG operation» → strange combination - problem/!\
  • «Delegate»+«Vector»+«Branch operation» → strange combination - problem/!\
  • «Delegate»+«Vector»+«INT operation» → strange combination - problem/!\
If imaging variant, where «ALU with Delegated Vector» is an external operation, like x86-Esc for FPU and other, we can finding good place for architecture scaling! :idea:
But I can't understand how it must working even on JavaScript-emulator! :roll:

P.S.: This architecture just looking as "wrong way", if You can't or don't want see "beautiful philosophy of concept".
But in other aspect - it looking like "fairy architecture", and it just fascinating! 8-)
Mon Mar 17, 2025 10:00 pm WWW
Alikberov
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Joined: Sat Feb 13, 2021 12:22 pm
Posts: 21
Location: https://en.wikipedia.org/wiki/Tashkent
Post WYSIWISC: What You See Is What It Should Compute
Eureka!
  • «Delegate»+«Vector»+«ALU operation» → analogue of «ALU Target,Segment:[Vector],Source»
  • «Delegate»+«Vector»+«REG operation» → analogue of «MOV Segment:[Vector],Source»
Normally, we have the AEN signal (Address Enable), but in the new case, we may also have DEN (Device Enable) too.
A simple system can ignore this, but in a complex system, it can form an extended address - A16-A31 (in an 8-bits architecture).

Then we have also
  • «Delegate»+«Vector»+«Branch operation» → branch if Delegated Segment is responsive
  • «Delegate»+«Vector»+«INT operation» → interrupt if Delegated Segment sent a request

It''s very elegant solve! 8-)
Mon Mar 24, 2025 2:00 pm WWW
Alikberov
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Joined: Sat Feb 13, 2021 12:22 pm
Posts: 21
Location: https://en.wikipedia.org/wiki/Tashkent
Post WYSIWISC: What You See Is What It Should Compute
Early I developed Verilog-model of "vector calculator" - one of difficult parts of CPU.

In present time I developed the draft in the Logisim:
Attachment:
Index.png


Animation of work:
Attachment:
example.gif

This draft is useless for CPU-Core - for visual testing only!
It's just beautiful!

Emulator on i8080:
Attachment:
Vector.png


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Thu Mar 27, 2025 6:00 pm WWW
Alikberov
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Joined: Sat Feb 13, 2021 12:22 pm
Posts: 21
Location: https://en.wikipedia.org/wiki/Tashkent
Post WYSIWISC: What You See Is What It Should Compute
The basic principles of operation of the prefix stream parsing node can be understood from Online Delegate Calculator.
the circuit generates ROTATE and SHIFT signals respectively with lines is_rotate and is_shift of the algorithm.

With this code:
Attachment:
DELEGATE.RKR.zip

You can also check the work in the online emulator i8080.
(Keys 0-9 and SPACE BAR for clear)

The closest reverse analog of my circuit is the DM2504 or MM54C905.

  • C - Clock input (posedge - positive edge)
  • S - Mode selector (active level - low)
  • EN - Enable operation (active level - low)
  • EB - Enable base latch (active level - low)
  • IC - Instruction Code: Bits 4…7 - input
  • B0…B3 - Base (base register index output)
  • EB - Enable Base (enable base register index latch)
  • ROTATE - Output signal for index entry scrolling («index <<= 1») - index repeat
  • SHIFT - Output signal for index entry expansion («index += register») - enable entry

P.S.: VIDEO


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Sat Apr 05, 2025 4:00 pm WWW
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