As for the writeback stage, without getting into too much detail, it's common to build register files with synchronous RAM in an FPGA. This means you need a clock pulse (usually the inverted cpu clock) for the RAM to do a write and to register the read address and perform the read. So that means you need to have the value you want to write early in the cycle, hence needing the writeback stage. Further, the read value is only available very late in the cycle, so it would be very tight to add muxes after the register file, and often then you would put all the muxes at the beginning of the execute stage instead.

...It seems to me that you can place the muxes at either the beginning of the execute stage or at the end of the decode stage, for example, and this works whether you have a WB stage or not. Each approach simply affords a different tradeoff in terms of how delay is distributed between pipeline stages, that’s all.

One can also extend the pipeline by a cycle or two and use additional results forwarding after the writeback-stage to compensate for a two-cycle read latency of block rams. Data ends up coming from results forwarding latches while the register file output is still invalid. This allows the use of the regular clock, no inversion needed, and the value to write can be later in the cycle.