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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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Quote: What about anti-aliasing character bit maps? I think anti-aliasing uses shades of grey, alpha blending, around the jagged edges of a character to make things appear smoother. The editor does not support editing this style of bitmap character. The Editor is basically only two-color. It would be a chunk of work to support automatic anti-aliasing for character images. The author wanted the editor for creating fonts for the TextController component assuming limited memory resources for images. I suppose a mode for anti-aliasing using four colors could be added to the TextController. In theory GlyphEdit now supports .bmp, .jpg, and .png formats. It should be possible to load a bitmap with fonts then save it in an available format. This should allow creating a font in a paint program of some sort. The very first pixel of a bitmap is assumed to be the background color. Bits are then checked against the background color to see if they should be clear or set. _________________Robert Finch http://www.finitron.ca
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| Mon Oct 10, 2022 8:46 pm |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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Pulled the I$ code out of the BIU into its own module. D$ code will be next. About time I did this.
Added anti-aliasing feature to the text controller. It uses bit pairs to allow one of four levels of blending background and foreground colors. 100%, 66%, 33% and 0%. Anti-aliased bitmaps take twice as much memory as non-anti-aliased ones. While the hardware may support it (it is an config option) the GlyphEdit program does not have this feature fully implemented yet.
_________________Robert Finch http://www.finitron.ca
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| Tue Oct 11, 2022 4:21 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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Finally got around to updating the sprite editor portion of the glyph edit program. Tested the sprite image on a real screen. It looks like the sprite may be missing pixels; however, the image looks to be the correct size. Then it occurred to me it may be the display device, a TV. I think also that pairs of pixels may be swapped.
The sprite editor is still clunky. If the sprite size is not set before loading a sprite file the editor crashes. Meaning it is necessary to click on the size numeric up-down controls before loading the sprite. Changing the size of the sprite after load likely leads to a crash. The editor can save or load images in .bmp, .mem, .coe, .bin and even ‘C’ source code format. An image created with the editor was loaded into Paint3D as a test.
The great feature of the editor is being able to load a .bmp and save in a .coe or .mem format. The latter formats needed to load into block RAMs.
The editor allows editing the entire sprite image cache. The image cache may contain multiple sprite images. Each cache is 4096 bytes in size. So, it may contain one image at 56x36x16bpp or eight images at 16x16x16bpp. Image size is flexible.
The sprite controller allows selection of an image from the cache. By cycling through the image selections simple animations can be done. The animations have low CPU bandwidth requirements as no memory is being transferred. It is just a pointer update in the sprite controller. I think using image caches for the sprite data is the way to go. It offers higher display bandwidth than a direct DMA from DDR memory while using less memory bandwidth.
_________________Robert Finch http://www.finitron.ca
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| Thu Oct 13, 2022 4:16 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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A screenshot of the Sprite Edit Screen. Long way to go yet, but usable. Attachment: SpriteEditScreen.png
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_________________Robert Finch http://www.finitron.ca
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| Thu Oct 13, 2022 4:24 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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Added the ability to animate sprites in the sprite editor portion of GlyphEdit.
Added animation ability to the sprite controller hardware. It can now cycle through frames of images to produce simple animations. It does this automatically without CPU intervention.
Animation frames must be at least a multiple of two pixels in size, due to limited number of bits in the animation register. The number of frames of animation can be specified, up to 256, and the frames remaining in the image cache not used for animation. There can be multiple animation sequences in a sprite image cache, and the sequence selected by the sprite image offset register. Animated sequences are relative to this register.
I made a little demo of a butterfly with six frames of animation. The animation is not quite correct yet. One thing is I set the frame size incorrectly to 16 pixels when it should have been 256 pixels, as the butterfly is a 16x16 pixel image. The image is also a bit garbled. Time to make a red-box image.
_________________Robert Finch http://www.finitron.ca
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| Sat Oct 15, 2022 4:05 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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The most recent major change to the ISA was to use 48-bit instructions instead of 40-bit ones. The wide instructions give a few more bits to allow any register to be used as a mask register. And also allow a few extra bits for the constant field of an instruction. 64-bit constants can now be encoded using only a single postfix instruction. The instruction size field was also expanded by a bit to support more sizes. Byte size operations are now present in the ISA. Additionally instructions are aligned on 16-bit boundaries now instead of byte aligned. This may help decoding in the future.
Some work on memory loads today. Load requests were not recording the target register, so when the load finished no register update took place and the machine hung waiting for the target register to be updated before issuing subsequent instructions. That is all fixed up now, so the machine goes through the load process. But it is not reading data properly through the cache yet. A memory load request can be seen at the memory itself fetching the correct data, but somehow the cache does not get updated. More work to do yet.
I believe the machine now properly sequences through the Fibonacci but comes up with the wrong results due to loads not working correctly.
I made a brief movie showing the sprite controller in action, but the movie quality has some to be desired. It is about a 10 MB file.
_________________Robert Finch http://www.finitron.ca
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| Thu Oct 27, 2022 3:56 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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More work on memory loads. Memory data now makes it into the cache but there are issues yet with the data making it to the register file.
_________________Robert Finch http://www.finitron.ca
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| Fri Oct 28, 2022 4:15 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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Had to modify the pipeline to stall on stores with overlapping address ranges. Only one store for a given address range may be in the pipeline.
There is still some sort of load / store issue where values are not being updated properly. Mode debug code was added.
_________________Robert Finch http://www.finitron.ca
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| Sat Oct 29, 2022 3:46 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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Lost the hard drive over the weekend, and a *lot* of work with it. I had the most critical stuff backed up. Restored some from backup. But I lost things like my test benches. I had over 1TB of data. So, it is slow going to rebuild things. Lost numerous directories of projects I never bothered to back up because I figured they were not going anywhere. Lost most of my test systems, because I figured if I lost them I could rebuild from the components which were backed up. Had to fix the PC by installing a new SSD drive. Had to reinstall vendor and development tools. Now I am thinking of using cloud storage which would backup everything. Given that there seemed to be issues with the load / store test program I decided to try something simpler. There is an issue with marking registers busy or not busy and performing branches. It looks like rollback may not be working properly. I wrote a simple program to add numbers for processor testing. It successfully adds a linear list but when a branch is involved the core hangs waiting for a register to be marked not busy. Code: Source: "add.asm"
1: # add test rfPhoenix asm
2:
3: .bss
00:00000000 00 4: .space 10
00:00000001 *
5:
6: .data
01:00000000 00 7: .space 10
01:00000001 *
8:
9: # .org 0xFFFFFFFFFFFD0000
10: .text
11: .align 1
12: start:
02:00000000 890040230101 13: LDI r2,0x1234
02:00000006 444010000001 14: ADD r1,r2,1
02:0000000C 442010000001 15: ADD r1,r1,1
02:00000012 442010000001 16: ADD r1,r1,1
02:00000018 442010000001 17: ADD r1,r1,1
02:0000001E 442010000001 18: ADD r1,r1,1
02:00000024 442010000001 19: ADD r1,r1,1
02:0000002A 442010000001 20: ADD r1,r1,1
02:00000030 442010000001 21: ADD r1,r1,1
02:00000036 8900A0000001 22: LDI r2,10
23: loop1:
02:0000003C 442010000001 24: ADD r1,r1,1
02:00000042 8440F0FF7F01 25: ADD r2,r2,-1
02:00000048 9C0000FD7FE1 26: BNE r2,r0,loop1
27: mismatch:
02:0000004E 190000000001 28: BRA mismatch
29:
30: .balign 0x100,0x0B
31:
32: It loops once then hangs. _________________Robert Finch http://www.finitron.ca
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| Tue Nov 01, 2022 4:21 am |
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BigEd
Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1821
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Oh no, sorry to hear about the drive failure and data loss. Backups are quite irritating but eventually, often, also quite useful. I have only a patchy coverage myself, but I like to think I wouldn't be too badly hit.
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| Tue Nov 01, 2022 6:08 pm |
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Ken KD5ZXG
Joined: Sat Sep 03, 2022 3:04 am
Posts: 51
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Relative or absolute? Either way, I don't get 190000000001.
02:0000004E 190000000001 28: BRA mismatch
The BNE before it might not have assembled right either...
Your origin was 0xFFFFFFFFFFFD0000, and jumping a few steps backward, I would expect to see more F's.
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| Tue Nov 01, 2022 6:18 pm |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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Quote: Relative or absolute? Either way, I don't get 190000000001.
02:0000004E 190000000001 28: BRA mismatch
The BNE before it might not have assembled right either... Good catch. It looks like the instruction is not encoded properly for an unconditional branch. The displacement should be all zeros to branch back to the current instruction. The docs need to be updated to reflect changes to branches. The most significant bits of the conditional branch instruction are used to encode the branch condition and the operation size for the comparison. Six bits are used for this, and three more bits are unused. The branch displacement is still 19 bits. The 'E1' at the end is condition #7 (not equal) and size 2 (32-bit). After that is a string of ones '7ffdf' which is the displacement. Hmmm. Looks like it is encoded as -32. It should be -12 I think. I will need to run it in simulation again to verify. _________________Robert Finch http://www.finitron.ca
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| Wed Nov 02, 2022 3:50 am |
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