I foobar ed the card, nothing works.
I finished the new mother board, not reading memory right.
Hacked on a micro-SD card, hope to read that
soon.

Had to add a new instruction DJP Decrement and jump not zero, for fast looping. 4 cycles rather than 8.
Now 1.5 uS memory cycles. Bit banging routines to initialize the SD card seem to work. 6 blocks of 1K per track.

UPDATE.
revised the irq service logic.
added a single word software trap.
Final instruction set for now.

Added jump indexed.
Hardware is mostly done. I need to come up with a bootstrap-able language under dos.
A 16 bit K&R C most likely will host compiler.
Two pass, pass #1 syntax check recursive decent. pass #2 code gen.
; is end of statement. stropped keywords.

Revising the order code from 7 general purpose registers + PC
to 8 general purpose registers + PC. Had to do a some wire changes
to the ALU PCB.

Revised the 18 bit computer mother board and front panel.

I like the 18/36-bit size, but for floating point 32/64 bits works well. It is difficult to get approximations more than 8 or 9 bits in a single clock cycle for some of the fp operations. 6 or 7 seven-bit approximations for the fraction are easier. Even if the fp is another size, the bits approximately typically go 8/16/32/64, etc. For a simple CPU integer and fp busses will be the same size, so 8/16/32/64 for integers as well.

For a CPU using modern technology, it does not make sense to develop something with less than 32-bits, other than for maybe some specialized embedded applications.

18 bit floating point 1-6-11 for sign, exponent, and significand may work well machine learning type applications.

I have 18.18 fixed point arithmetic in Q+ for the graphics/neural net functions. I assumed plots would happen in a graphics area with 16-bit X,Y, and Z co-ordinates. 36-bit floating point might work okay for this. I would use 1-9-26 for the s,x,s.
More than 32-bits may be needed for addressing.
Off to design my own 36-bit CPU now, geared towards graphics / machine learning.

If the machine learning is handled by hardware networks, then maybe the CPU does not need a lot of registers. It needs only enough to be able to transfer data to/from the neural network hardware.

Right now, a clean simple 18 bit ALU is the best I can do. A 36 bit design microcode will not fill into the control CPLD
and still have BYTE addressing. Once I get a stable motherboard and memory with IO working, then I can play around with different CPU designs.
For floating point, I found this paper.
https://www.deepdyve.com/lp/association ... kxWPDdIfcS 27 bits are not enough for 8-digit accuracy
I think they may have learned more about real brains in the last few years, that computer neural nets original concepts may need to be revised.

Revised the order code to have 7 more registers.
They can be used as index registers, or loop counters.
I have 7 GP registers B C D W X Y S, 1 A reg, 1 PC and B' C' D' W' X' Y' S' limited registers.
S' is the stack frame pointer.

The logic of the last design had a bug some were, so I hard to roll back a bit.
Now I just have 8 registers and the PC. A B C D W X Y S,PC. Now I have a
frame pointer - W.
Software wise I have the basic raw serial I/O working and the bootstrap loader.
The SD card interface is now seems to work, int disk, read or write a sector.
A sector is 256 9 bit bytes.
Math routines have been revised, but small C has not been updated.

Thought of a better way to decode, so now I have 16 registers. The 7 extra registers is good for the odd extra counter or
scratch variable. Block size is 768 bytes @ 4 sectors per track. The IBM 1130 had 640 bytes per sector and 4 sectors per track.
Serial is 1200 baud, so it fits with 70's era computer. Memory is 1.6 uS cycle time.
New mother board and front panel are being shipped. I hope to have them mid week.If they work, I hope to have a stable computer hardware build.

Added ATX instruction for indexing by 2. R = R + (efa)<<1
I have all the standard instructions, filling up the opcode space. Now to work on software.

It is looking a bit like an x86 without segmentation. A,B,C,D corresponding to AX,BX,CX, and DX. X and Y corresponding to SI, DI. It also looks a bit like the 6809. Good for a late ‘70s era CPU.

Oddly this project started as x86 replacement, 8,16,32 data bits, 20 bit addressing as a Altera FPGA design.
The original plan was to have the fpga emulate 22v10 and 74ls181's and then later build the design in real hardware.
Sadly all my designs had problems routing, make a small change and it stopped working. Roll back and it still don't work

I tried some 2901 bit slice alu designs but I had mother board problems. I can read/write from the front panel but
not run programs. I decided to try using a 68k single board computer to emulate something. Once it arrived I started
looking for docs, and noticed a CPLD programmer was on sale.

This let me still have programmable logic, but CPLD's have fewer routing and timing issues. This time the goal was
computer something more complex than the IBM 1130 computer but simpler than the PDP-11. 18 bits was picked
because I wanted 36 bit floating point,and the bus just fit on a 60 pin connector.

Now that I have hardware working for reading/writing a SDC card, need to get a simple OS written for 70's hardware.
I get 1.2 Mb on the each platter disk, and I have 2 drives. A weird size using simple encoding. Double density will get me
2.4 Mb.

Decided to clean up the order code to be more like the 6809 for the new test version. I/O will still bit bang the SD card,but no rush for updated hardware.Changing jump condition to branch condition and adding branch to subroutine.
The older version will remove IRQ service for now and other extra functions.