Replace your IBM 7090 computer today, with the JCN 7069 system
A 36 bit machine you can hold in your hand,or foot like Joe the Gorilla.
With 4D pockets for coding sheets,Banana's, Pizza or Dr Pepper for ease of programing,
Patents pending. Coming early 1969. Why have 12 bits with a PDP 8/i when you get 3x more
at only twice the price.
Compare a 2.0 uS cycle time 7090 vs 2.5 uS for the Wonder Machine 69 that will fit
in your room not a Data Center.
Get yours today. reader card #0123127

With a 13 mhz osc, I can get a ~ 1.25 uS memory cycle. At any other speeds builds crash
or only work for a short time. I am nearly finished with this Micro Giant Brain design
and now in the testing phase.
PS: Testing the 16 Mhz version, 500 ns. 1.0 uS cycle -- Real brain speeds now.

Wonder Machine 69 is now out. This has a revised micro code for a more 60's instruction set and timing.
Running at .5 uS cycle time all day with out error it looks to be finished design hardware wise.Interrupt service
is possible but untested.
Now I need to get back to writing software.

Changed LEA (load effective address) to AEA (add effective address) for array indexing.
Frame pointer W has a change in decoding.

Progress is slowly going on a C like compiler- Sea. Can't write code too fast or I will get C(sea) - sick.
Just ample logic to self compile. The goal is 32KB in size;
PS: FEB 20,2026 prototype is working. Now I need to go back and add better error handling and valid includes.

The modified C prime number sieve is working. Takes more time to load than to run.
2 minutes to load, 15 seconds to run. A real C compiler for a Z80 is about the same speed.
Sieve for the 18 bit cpu, 30 seconds.

The bootstrap compiler can compile itself. Some changes need to made to get back to vanilla code
from the modern C format as I don't use CPP and long long. Code wise it is about 24Kb not including the stack.The windows executable is about 64Kb.
Now I need to go back and write the file system.
Ben.

> The bootstrap compiler can compile itself

Excellent milestone!

I still need to do more work at the BIOS level of software, with console and reading of disk blocks.
Most of it is rewriting for the new calling format, and some C string functions.
Software wise, I am at the level of a FORTRAN IV compiler, with no floating point,
so wring something new makes more sense than adapting code.

Spent all week tracing a bug in reading bytes but not words. Moved to a open collector bus and a 11.0592 Mhz osc,
This gives me a fudged 1.5 uS memory cycle.
I can't build a stable IRQ service version. The non service version seems be working, even after taking a comfort break.
110000 will soon roll down to 107777.

Revised the irq logic. and testing it now. This may may be a stable release.Now back to software after hardware changes.
I will write the file system now the high level language, I have rather than in assembler.
Simple text editing will let it be added to the rom bios assembler file.

Another dud, CPLD found. Slowed things down for a .8 uS cycle time for better pull up on the OC bus,
I am thinking having byte memory address is a bad idea. Word addressing is better, with the carry flag as the byte high,low flag.
The problem is that it will require a whole new set of pcb's and micro chips. $1500 I am guessing here,
The front panel stays the same.

It almost works. Need to play around with builds. Ordered a 4 Mhz osc, so the build will be more in the late 60's timing
like with the IBM 1130.
2 uS core memory cycle. Exact timing depends on what compiles.

The bad bit, decided to stay stuck so I then could remove things until it worked. Hmm a empty case.
It seems to have been a tri-state problem from the switch inputs. Replaced the 22V10's
and removed a pull-up resistor to 5 volts on tristate enable. Back to my 999 bottles of beer on the wall test program.

Needed to add reset to disable the 22v10 output at boot time. Seems to be working now.