My new design project is a stack computer named MAX built using TTL integrated circuits. This project has many similarites to other projects I have described here: The TTL-Retro, the LALU Computer and my recent experiments with the Harris RTX2000 CPU.

Stack Computers are natural Forth machines. While exploring the RTX2000 two things really stood out: Direct Threading and Machine Opcodes corresponding to Forth Primitives. Writing assembly code by hand for the RTX approaches coding in Forth. Direct threading is a very powerful hardware feature.

My goal with MAX is to create a computer from scratch which can be programmed directly using opcodes corresponding to Forth instructions. Higher level Forth instructions can be created by using the direct threading.

I've decided to start simple and work with an 8 bit machine. (The TTL-Retro was a 12 bit machine, and LALU was a 16 bit machine.) You might say MAX will be a canonical stack machine built in hardware. The CPU will be my own design burned into ROM, similar to LALU. The ALU will start by simply using NAND IC's, and likely progress to a Lookup Arithmetic Logic Unit (LALU).

I plan to make provision for multiple stacks: Data, Return, Code and Keyboard. The Code Stack holds the program code. The Keyboard stack handles Input/Output to the operator, which can be a serial stream.

The MAX design will be using TTL. A key learning for me has been the realization of the efficacy of using negative logic. NAND gates and active lows are your friend! It really is amazing how much simpler things become regards the glue logic.

Anyway, that's the plan. More to follow regards the hardware. Michael

Certainly sounds interesting... how is the user's serial I/O a stack though? It feels like it needs to be a queue.

Yes, the Keyboard Stack is used as a queue by resetting the counter after the input text stream has been received. (FIFO instead of LIFO)

To minimize construction costs I decided to use a standard 100mm square size for the MAX PCB's. This size allows purchase of 5 boards for $5, plus shipping and tariffs, from PCBWAY. Each board of MAX has a 50 pin connector to the bus, which is simply a passive backplane.

The first board I will describe is the Clock/Oscillator board. I am using a canned 1 MHZ oscillator as the timebase, and generate 6 rings or phases using the circuit shown in the attached schematic. There is nothing special about this design, and it is similar to what was used on TTL-Retro and LALU.

I also generate a quadrature clock for the bus, which can be a convenience for some of the TTL glue logic. I used an oscilloscope to verify the pulses are correct, and that the reset circuit works correctly. Unused board space was filled with prototyping work areas.

Real men use a 74H04.
A 4.92 Mhz or 1.288 Mhz osc could be a better choice if plan to have a serial device or some sort of time generation logic,
Remote single step ,and single clock step could be option for later system debugging.
The only major fault I see is no power on reset, with a 555 timer.

Here is an update on the MAX Stack Computer. Attached are 2 photos: The MAX computer assembled, and the individual boards. At the moment we have: Clock Card, Data Stack Card, ROM Stack Card, Controller Card, ALU Card, and Bias Card. Probably the most significant mistake was reversing the data line sequence on the ROM stack (fixed with ribbon cable.) The Bias Card is useful for development because I can bias bus lines High or Low depending on my tests. I am using a programmed ROM for the MAX controller. I expect to split the controller into two ROM's going forward: Hardware Controller and Stack Controller.

I have spent a lot of time experimenting with the architecture. I have decided to use the A register on the ALU as the TOS (Top of Stack). I am also still evolving on the exact format for the 8 bit instructions. I also want to incorporate stack counter presets loaded from the bus for jumping, and other purposes. At this point I plan to clean up the circuit diagrams, fix the PCBs and do another spin from here. Michael

Looks very nice.

That's not a great comment Ben. People make the projects they want to make.

Hello! I continue to work on the the MAX Stack Engine Computer. I've found several mistakes in the PCB layouts while testing. I recently purchased a used Tektronix Digital Oscilloscope, which has been very helpful for troubleshooting.

I am using a pair of 27C64 programmed ROMS for the hardware controllers. I have found that the fastest 125 ns devices are preferred to minimize glitches during state transistions with my 1 MHZ clock.

Using NAND gates for the ALU was intended to be a temporary measure, although now I have come to appreciate their versatility. My next ALU improvement may be a hardware bit shift. Using a single zero detect on the Top of Stack is a convenient way to implement conditional jumps.

Lately I have been programming the Forth Primitives using my Excel Spreadsheet composer. I have been methodical about testing each primitive. I have not yet implemented direct threading, but have a plan for doing so with hardware.

Attached is a simple diagram of the MAX architecture. It's nothing fancy, but I'm happy with it. Michael

Here is an update on the MAX Forth Engine project. I continue to iterate on the exact details of the circuitry and PCB implementation. Concurrently I am coding the Forth instruction set. I have created a summary sheet of the instruction set to date, which includes the instruction, stack diagram, mnemonic and hardware control signals, which is attached.

The controller ROMS are programmed using my Exel based composer tool. Having the hardware control signals identified, I can modify the default signal outputs per desired control actions. The top of the tool lists the signal inputs, followed by hardware output controls. I shade the cells with the relevant operations. By using 2 control ROMS I can pretty easily keep things in manageable form regards the practical matter of scrolling in the spreadsheet, etc. Burning a ROM is a simple matter of cutting and pasting the last column into a binary file. The instruction shown is for NOT, which is a double NAND in Ticks 3 and 4.

Also attached is a rudimentary timing diagram. Ticks 1 and 2 are for instruction fetch. You can see in the example I perform hardware control operations in Ticks 3 and 4 for the NOT, aligned with the text descripton for instruction 01. Right now I am using 4 bits for instructions (out of a possible 8). I likely will expand to 5 bits soon. Reserving the other bits for future uses. Michael

Here's a simple thing that has been helpful during MAX development: A hexadecimal display showing the byte on the Top of Stack (TOS). Created this plug and play board to continuously display what's there. Simple and useful. FWIW. Michael

I do like a bit of instrumentation!

Development continues on the MAX TTL Forth Engine Computer. The passive backplane has expanded to 11 slots, which I use to mix and match various function cards at will.

The clock and ring counter board was modified to include a series resistance array to reduce ringing. There are now 2 ALU boards operating in parallel: NAND (original) and FULL ADDER. The main controller card now uses M27C256B devices, which are available in 70 ns speeds. A memory card using SRAM has been added. Also new is an output card, which basically is a register attached to hexadecimal LED display.

In the works are a parallel input card with A/D converter. Also a decade counter card. (Each bit from the counter card increases by a factor of 10, with a range from 10 us to 100 sec.) Also coming is a card to provide a dedicated bus register. (Helpful for coding some of the more complex Forth primitives such as ROT.) Also in the works is an Auxillary Controller card, which will work in parallel to the existing controller. Finally, I am still considering adding a LUT card, which would be helpful for bit shifts, bit manipulation and translations, even in unary mode. (Function of TOS only)

I am considering several different number representation schemes, some are pretty wild. I currently have 22 Forth primitives.

Here are some photos of the assembly, and a subset of cards that I am using. Progress has been paced primarily by the delivery cycle for PCBs using snail mail from China. I also have been more rigourous than usual about testing and creating schematics as I proceed. Michael

The MAX computer has progressed to the point that I would like to share some of the design details. I am going to start with the cards I've been tempted to call "Stacks", but they are not strictly LIFO unless I intentionally use them that way. The cards I have are Data, ROM, Return and Memory. All 4 cards are very similar in design, so I am going to describe the Memory card.

Every card has a dedicated 8 bit TTL counter that can be incremented, decremented, loaded and read. The counter provides the address to the SRAM. So to read a value of memory you would load the counter with the address and read the SRAM.

You can also use the counter as a counter. So in that case you load the counter, increment or decrement, and read the result. You can also use the counter to sequentially read data going forward or reverse. (More on that later)

This same card architecture is used for the other cards. The controller sends a 'select' (S1,S2,S3,S4) signal to indicate which card is the target of the hardware instructions from the controller.

You can probably guess some of the differences between cards. You obviously can not write to the ROM card. The Data Card has a register for the TOS, with it's own control signals. The Return card has a slight twist in that I made reading the return address a direct hardware signal, since it is not allowed to address 2 cards at the same time. (Return requires reading the return address AND writing the counter of the ROM card.) Here is a diagram to convey the general idea.

These are my go-to parts doing TTL. The 74LS30 is actually a pretty useful item for zero detect and decoding. (8 input NAND). For my counters it would have been nice if there was a full 8 bit counter chip. I pretty much always use the 244 buffer and the 373 latch. This series is pretty darn robust. Even with all my wiring mistakes, etc they take a beating and keep on ticking. For the ROM controllers I always use the fastest chips I can find. My system clock is 1 MHZ.

Here is a list of core TTL ICs that I have used for the MAX project:
74LS153 Dual 4-1 Multiplexer, Flag control
74LS169 4 Bit Syn Up/Dn Counter, Stack Pointers
74LS244 Octal Non-Inverting Buffer, General Purpose
74LS283 4 Bit Binary Full Adder, ALU #2
74LS373 Octal Transparent Latch, General Purpose
74LS390 Dual 4 Bit Decade Counter, Decade Clock
74LS688 8-Bit Mag Comparator, Zero Detect

Memory
MCM6264C SRAM, Stacks & Memory
27C256 ROM, Programmable Controllers
27C64 ROM, Program Code

Logic Glue
74LSOO Quad 2 Input NAND, ALU #1 & Glue
74LS04 Hex INVERTER, General Purpose
74LS08 Quad 2 Input AND, General Purpose
74LS30 Single 8 Input NAND, Zero Detect
74LS32 Quad 2 Input OR, General Purpose

Crystal Clock Oscillator
74HCT4017 Johnson Counter, Ring Generator
74HCT244 Octal Non-Inverting Buffer
74HCT04 Hex Inverter, Inverted Clock