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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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I have revised my 20 computer for 18 bits, as virtual machine in C.
I have few bugs still with it but the printf is now working.I can debug!
Most of the bugs were going from hex to octal constants. File I/O still needs work.
Once this working I will upgrade to a 36 bit version. Findng software to port may be a problem
as I needed a 16 bit compiler with longs.
Hardware wise I have the basic logic for sketched out for 36 bit cpu running twice
thru a 18 bit alu. Logic uses 128 cell cpld's and 16x9 ram. 1 74LS14,1 OSC.2 74F74's ,3 1508's
and 2 82S09's make up the hardware ALU.
4 22v10's, 555 timer and a debounce chip make up the a 5 slot mother board,
with a 6 octal led display and switches.
The end goal is a late 60's cpu design to compete with the IBM 11:30, DEC PDP 11 and DEC PDP 9
and use similar memory & I/O hardware of the time. pdm -9 ( Programed Data Machines ).
I have it all planned. Ben-gates logic,Benux operating system,Bengol Compiler,Benware (software).
This really is a retro project,of a computer in some form using the surplus parts of the 70's that
I never quite had the money for or the room to keep vintage stuff around, or 3 phase power.
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| Wed Aug 21, 2024 4:52 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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Sounds a bit like the 68k, running data through a 16-bit ALU twice.
A retro design.
_________________Robert Finch http://www.finitron.ca
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| Wed Aug 21, 2024 9:42 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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robfinch wrote: Sounds a bit like the 68k, running data through a 16-bit ALU twice.
A retro design. Shifting is limited to ASR,SZR,SCR,SZL,SCL, since I don't have the other end for rotates. SZL R ; ADC R #0; is a easy subsitute for ROL R. I am having problems with the gets function, but other than that it seems to be working for the 18 bit version. Changing from ints to unsigned longs made a big speedup in the code. Going to 36 bits is just adding the two 36 bit memory instructions. The cross assembler only handles 18 bits, so 36 bit data needs to split up as two words. The 68K cpu I plan to test the virtual 18 bit machine only has 1 meg of ram so I just have room for 256Kb of emulated memory.
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| Wed Aug 21, 2024 1:27 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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The gets problem was hex to octal conversion error.
I revised the order code,so I will be working back on the 18 bit stuff.
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| Fri Aug 23, 2024 8:17 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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I am using a 1508 CPLD (128 macro cells) to do all my control logic including the 256x16 proms.
This is fittng for the 18 bit simple version, but upgrading for the larger 36 bit control I run into problems. I have no idea where the problem is, as the fitter software crashes with no error messages.
I am going to take a closer look at small 20 bit cpu using the same order code layout, as the 36 bit version is on hold.
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| Sun Aug 25, 2024 9:53 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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Since I removed long opcode decoding, I tried to add floating point traps for floating point.
Push efa,call table [opcode]. Just too complex for the control CPLD after a few days work.
I got get this design out the door soon (Binary Computer 74) as it will be over 50 years soon.
I plan to use 48kb core ram and 4Kb core rom, that system to be about the price of a small house.
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| Thu Aug 29, 2024 7:58 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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oldben wrote: Since I removed long opcode decoding, I tried to add floating point traps for floating point.
Push efa,call table [opcode]. Just too complex for the control CPLD after a few days work.
I got get this design out the door soon (Binary Computer 74) as it will be over 50 years soon.
I plan to use 48kb core ram and 4Kb core rom, that system to be about the price of a small house. Looking at the fact I want to use a FAT style disk format, 1977 will give me ample ram and DDSD 8" floppies. Sector size is 1280 bytes per sector. 77 tracks 2 sides 6 sectors per track ~924 blocks, (using some sort of GCR) for floppies and 190 tracks, 2 sides 4 sectors ~1520 blocks for a RK05 platter. A directory entry is a 7.2 file name ( 3 words ) a flag byte and 3 fat entries (9 bit byte) for 3 segments of 510 9 bit block number. 0 and 1 reserved for Free and End, 1 word for byte count. ~ 100 entries per directory. (1 sector). FAT is 2 sectors.
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| Sun Sep 08, 2024 7:01 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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oldben wrote: Looking at the fact I want to use a FAT style disk format, 1977 will give me ample ram and DDSD 8" floppies.
Sector size is 1280 bytes per sector. 77 tracks 2 sides 6 sectors per track ~924 blocks, (using some sort of GCR) for floppies and 190 tracks, 2 sides 4 sectors ~1520 blocks for a RK05 platter.
A directory entry is a 7.2 file name ( 3 words ) a flag byte and 3 fat entries (9 bit byte) for 3 segments of 510 9 bit block number. 0 and 1 reserved for Free and End, 1 word for byte count. ~ 100 entries per directory. (1 sector).
FAT is 2 sectors. May go with 1K sectors, and 2K fat and 2K directory and 1 data buffer. ~16Kb for disk buffers. Right now I have the instruction set done, but not sure to focus development on a 18 or 20 bit cpu yet. With the CPLDs I am using I could even have a 22 bit computer, but other than packing 3 7 bit bytes per word I can see no real advantage.
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| Sun Sep 08, 2024 7:46 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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Need to look at the library functions for to update 16 bit word length constants a the new word size.
.
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| Mon Sep 09, 2024 7:57 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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oldben wrote: Need to look at the library functions for to update 16 bit word length constants a the new word size.
. Found the bug, used %X not %x for printf stuff. Emulator now puts the stack pointer at the end of memory 0BFFF (48K) not at (32K). The small C compiler ends at 0AE00. The cross assembler ends at at 07B00. No more stack in the in the middle of the code. The current format (pending more testing) is Code:
A 18 bit computer that grew
21 bit format - bit 21 reserved for expansion
20 bit wide memory / 10 bit bytes.
new format
21 111 111 111
09 876 543 210 987 654 321
+---+---+---+---+---+---+---+
|.#O|OOO:AAA|321|XXX:X@Y|###|
+---------------------------+
|.#O|OOO:AAA|..+|###:###|###|
+---------------------------+
original format
876 543 210 987 654 321
+---+---+---+---+---+---+
|#yO|OOO:AAA|321|XXX:+##|
+-----------------------+
|1.O|OOO:AAA|+##|###:###|
+-----------------------+
OP SH REG
0 ST Y P
1 ADC ADD 0 X Z abs
2 SBC SUB C W
3 CAC CAD S
4 ADX AND D
5 OR 0 C
6 XOR C B
7 LD S A
. BYTE % REG @ reserved
0 CTL control
1 LEA load effective address
2 JSR jump to subroutine (auto)
3 SWP swap indexed with ac
4 R+ store (auto)
5 X+# store indexed
6 R+ store (auto) byte
7 X+# store indexed byte
# JPR jump register
0 SCC# set logic cc to #n
1 SFT shift ac x 1
2 JCC jump on condition (auto)
3 REG reg operate
4 R+ operate (auto)
5 X+# operate indexed
6 R+ operate (auto) byte
7 X+# operate indexed byte
# # operate # byte
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| Wed Sep 11, 2024 2:31 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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oldben wrote: Code:
A 18 bit computer that grew
21 bit format - bit 21 reserved for expansion
20 bit wide memory / 10 bit bytes.
new format
21 111 111 111
09 876 543 210 987 654 321
+---+---+---+---+---+---+---+
|.#O|OOO:AAA|321|XXX:X@Y|###|
+---------------------------+
|.#O|OOO:AAA|..+|###:###|###|
+---------------------------+
original format
876 543 210 987 654 321
+---+---+---+---+---+---+
|#yO|OOO:AAA|321|XXX:+##|
+-----------------------+
|1.O|OOO:AAA|+##|###:###|
+-----------------------+
OP SH REG
0 ST Y P
1 ADC ADD 0 X Z abs
2 SBC SUB C W
3 CAC CAD S
4 ADX AND D
5 OR 0 C
6 XOR C B
7 LD S A
. BYTE % REG @ reserved
0 CTL control
1 LEA load effective address
2 JSR jump to subroutine (auto)
3 SWP swap indexed with ac
4 R+ store (auto)
5 X+# store indexed
6 R+ store (auto) byte
7 X+# store indexed byte
# JPR jump register
0 SCC# set logic cc to #n
1 SFT shift ac x 1
2 JCC jump on condition (auto)
3 REG reg operate
4 R+ operate (auto)
5 X+# operate indexed
6 R+ operate (auto) byte
7 X+# operate indexed byte
# # operate # byte
The 20 bit cpu was just a little too big, for the mother board layout. The 18 bit cpu fits smaller. Use EXG (exchange reg) instead of JPR. (jump reg)
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| Thu Sep 19, 2024 8:25 pm |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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One chip less. More room for routing.
It is almost 5 x 7 inches, but the stupid metric kicad has it 5.0039 and 7.0039. inches.
Mother board is 6.2539 and 5.2539. Stupid creep.
Control logic, does not permit a swap but a EXG (exchange) is still possible.
One CPLD is control and the other two are 9 wide bit slices. 74LS189's is the internal
ram.
Memory 8Kb ROM and 256Kb RAM. Each card is 1 nine bit byte wide.
Summer 1974 was the planned release, but things have been delayed by a few decades.
Fall 2024 for the hardware, after more work on the 68000 emulation now that the order code
and memory layout has firmed up. I need still a simple operating system, but Small C is not
up to the task for the footprint I want.
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| Sat Sep 21, 2024 6:49 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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The CPLD design looks efficient for 9/18 bits computer, so I plan to try a long shot and go for a 22 bit binary computer. 11 (decimal) bit trinary computer?  Time for sleep , 1 sheep 2 sheep ... X sheep IX sheep 10 sheep. Code: 16 registers rather than 8.
Small Komputer 1974
2 221 111 111 111
2 109 876 543 210 987 654 321
+---+---+---+---+---+---+---+---+
|--O|OOO|#-A:AAA|321|-YX:XXX|###|
+-------------------------------+
|--O|OOO|#-A:AAA|0+#|###:###|###| QUICK
+-------------------------------+
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| Sun Sep 22, 2024 4:39 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am
Posts: 2307
Location: Canada
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At 11-bits it could make use of 16-bit RAM wide with 5 ECC bits.
I had thought of making a CPU with 10-bit bytes, using ECC on the RAM access.
_________________Robert Finch http://www.finitron.ca
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| Sun Sep 22, 2024 6:07 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 768
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robfinch wrote: At 11-bits it could make use of 16-bit RAM wide with 5 ECC bits.
I had thought of making a CPU with 10-bit bytes, using ECC on the RAM access. Most static memory now has error correcting built in. Not sure what modern dynamic memory does. Error correcting memory needs to be scrubbed every so often. This might be a good thing as one could do hardware garbage collection at the same time as well as virtual memory processing like access flags updates. Core memory needed ECC just because it was often pushed to the limit for speed, and any noise could set things amuck.
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| Sun Sep 22, 2024 7:15 am |
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