Here is a link to my a working 6809 machine in a $30 Tang Nano 20K FPGA board.
https://tildegit.org/potato/TangNano20K-6809
* 27MHz (should be good to 40MHz or so).
* 64K RAM
* 115200 serial
* 6 LEDs
* Reset button
* Loader (see boot.asm and test.asm)

It's a minimal effort but it runs.

Reset seems to be flaky sometimes requiring reconfiguring with OpenFPGALoader. Investigating this issue.

Nice! I see you have the p revision of the 6809 VHDL core - and there's an n revision here.

If you would like another 6809 core for comparison there is one https://github.com/robfinch/rf6809 written in System Verilog.
There is an option for 8/12 bits.

Have your considered packing the 12 bit CPU in a 40 pin FPGA module?

https://blog.paulsajna.com/fpga-mcs6530-rriot/

I am very curious about the 12-bit CPU, and will definitely give it a shot sometime later! It may be just the wingspan I've been looking for.

robfinch, since I have your attention, how do you connect your core to the BRAMS? To get this project to work with sync BRAM I had to use an inverted clock for the BRAM, which almost makes sense but makes me uneasy about the timing, especially for the IO mapping. What is your normal way to do it?

The core interfaces to external memory using a WISHBONE bus (see opencores.org). It has an internal instruction cache though to improve performance. The interface to BRAM should be fairly straightforward. Connect address, and data input. Then return an ack from the BRAM after a clock cycle. It may also work with an inverted BRAM clock and ack in the same cycle. But WISHBONE needs to see an ack signal.
I had the 6809 running a system-on-chip for a Artix7-35 48 pin module from Digilent (I forget the exact name). It was using the external 512kB SRAM memory. There is a controller for the memory in the SoC.
The project is here (including CmodA7 components)
https://github.com/robfinch/rf6809
Thanks for interest.