The computer is perpetually half done (it could be more it could be less, I only design the logic for the chunk I'm working on) but currently consists of about 300 transistors. I'm pretty sure that the computer follows 'Harvard architecture' (corrections welcome) as the RAM and ROM are strictly segregated. 4 bit is used loosely data width is 4 bits but instruction width is 8 bits as some instructions include 4 bit values.

some stats:
RAM: 16 nybbles (dictated by address register width)
ROM: 16 bytes (dictated by program counter width)
clock speed: more than one (the computer is currently not clocked as much of the sequential logic has yet to be built)