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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2307 Location: Canada
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Mainly fixed up the compiler today. There was an issue with nested array references. The compiler was not loading the value from the inner array to use as an index. This showed up in the following code, pgtbl indexed by a value from pte array. Code: for (cnt = 0; cnt < 24; cnt+=2) pgtbl[pte[cnt]] = pte[cnt+1];
The compiler was rebuilt for both Qupls and Riscv, but operation of the Riscv version is unknown.
_________________Robert Finch http://www.finitron.ca
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Tue Feb 13, 2024 10:13 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2307 Location: Canada
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Latest Bug Fixes The compiler was using the wrong overloaded function to output numeric values. This resulted in the numeric values being truncated for 64-bit values (the upper bits were removed).
_________________Robert Finch http://www.finitron.ca
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Thu Feb 15, 2024 3:14 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2307 Location: Canada
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Bugs are being pretty ornery lately, taking me time to fix. There is currently a bug in stack allocation for arrays declared locally. Not enough stack space is allocated, it is close but not enough. The latest bug fix was for array indexing. It looks like it should work at least for up to three dimensional arrays. The maximum number of array dimensions is nine. The following test program is used to test arrays. Code: integer main() begin char cha[25]; char a[100][10]; integer x,y,z; short integer si[20][30][40];
z = cha[13]; y = a[5][7]; y = 21; z = 7; x = a[y][z]; return si[12][13][14]; return (a[12][6]); end The following code is generated. Notice the stack allocation is 77160, but according to the size of the arrays it should be over 96000. (20*30*40)*4 array = 96000. Code: .data .align 6
.align 6 .text
;{++ _main
.sdreg 29 _main: sub sp,sp,32 sto fp,[sp] mov fp,sp sub sp,sp,77160 sto s0,[sp] sto s1,8[sp] ldo t0,[fp] ldo s0,-120[t0] ldo t0,[fp] ldo s1,-204[t0] ; char cha[25]; ; z = cha[13]; lda t0,-50[fp] ldw s1,26[t0] ; y = a[5][7]; lda t1,-90[fp] add t0,t1,50 ldw s0,14[t0] ; y = 21; ldi s0,21 ; z = 7; ldi s1,7 ; x = a[y][z]; ldo t0,[fp] lda t2,-90[fp] mulu t3,s0,10 add t1,t2,t3 asl t2,s1,1 ldo t3,0[t1+t2*] sto t3,-98[t0] ; return si[12][13][14]; lda t2,-77110[fp] add t1,t2,14400 add t0,t1,520 ldt t0,56[t0] mov a0,t0 .00010: ldo s0,[sp] ldo s1,8[sp] mov sp,fp ldo fp,[sp] rtd 32,0 ; return (a[12][6]); lda t1,-90[fp] add t0,t1,120 ldw t0,12[t0] mov a0,t0 bra .00010 bra .00010 .type _main,@function .size _main,$-_main
;--}
.global _main .extern _start_data .extern _start_bss .extern _start_rodata
_________________Robert Finch http://www.finitron.ca
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Sun Feb 18, 2024 3:21 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2307 Location: Canada
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Got the array size bug fixed. Processing array indexes in the parser needed to be improved.
Now adding support for Qupls40, which has only 16 GPRs. If the compiler runs out of temporaries it starts using callee saved regs.
_________________Robert Finch http://www.finitron.ca
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Mon Feb 19, 2024 7:18 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2307 Location: Canada
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Took a side trip trying to fix an issue where indexing was generating both a multiply and scaled indexed addressing. The index was scaled during the memory op, but also multiplied by the size. Only one or the other should be done. I had to back out changes, then reload and start over.
Latest change: - moving link registers to and from a general purpose register so that it can be saved and restored on the stack. - the link registers are not part of the general purpose array. They generally do not need arithmetic or logical ops performed on them. - having them separate from the GPRs effectively makes another GPR register available for use. - this is like the PowerPC.
_________________Robert Finch http://www.finitron.ca
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Tue Feb 20, 2024 7:39 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2307 Location: Canada
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Switching to using longer mnemonics for assembly language. “load” instead of “ld” and that sort of thing. It is a little easier to read the longer mnemonics and the assembler code is seldom read.
_________________Robert Finch http://www.finitron.ca
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Wed Feb 21, 2024 2:34 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2307 Location: Canada
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Added constant optimization of branches to the compiler. If two constants are being compared for a branch condition, then either an unconditional branch is output or no branch is output. Unconditional branches are faster than conditional ones because they are performed earlier in the pipeline. So, smaller and faster code results if constants are being compared. This happens fairly often at the start of loops with loop inversion. For the first iteration the value of the loop counter is known.
Improved the type coercion for expressions, still needs a lot of work though. Unless specifically indicated otherwise, the largest type between the two in the operation is returned. Ran into an old ‘I’ll get to it later’ bug. Constants indicated as unsigned with the ‘U’ appended to them were simply treated as signed constants, the unsigned indicator was ignored. For most constants this does not make much difference. But when shifting an unsigned value by a signed value, the wrong shift ended up being used.
_________________Robert Finch http://www.finitron.ca
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Thu Feb 22, 2024 6:06 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2307 Location: Canada
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The compiler croaked parsing a character string definition like: Code: const char *msgXmTimeout = {B"Xmodem: timed out",0x0D,0x0A,0};
It thought it was some sort of weird aggregate type when all that is needed is to concatenate all the string information. It was just a little bit more code to fix it up. Made a couple of other minor fixes too.
_________________Robert Finch http://www.finitron.ca
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Tue Mar 25, 2025 3:11 am |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2307 Location: Canada
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Upgraded the arpl compiler for the StarkCPU (Qupls3) to select predicate branches instead of ordinary conditional branches if the number of lines of code branched over is small ( < 7). It does this during peephole optimization.
Also disabled inlining of code for the StarkCPU. The ‘leave’ instruction needs to be adapted to support inline code. Inline code does not get much mileage in the StarkCPU, so it is simply disabled.
Found a bug in the compiler, assignments of constants to registers when the register is actually a pointer did not work. The compiler spit out a load instruction when it should have spit out a store instruction.
_________________Robert Finch http://www.finitron.ca
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Tue Apr 08, 2025 2:15 am |
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