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 "An Out-of-Order RiSC-16" 
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BigEd

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1874
Post "An Out-of-Order RiSC-16"
An interesting paper:
An Out-of-Order RiSC-16 (31 page pdf)
Quote:
Tomasulo + Reorder Buffer = Interruptible Out-of-Order
ENEE 446: Digital Computer Design, Fall 2000
Prof. Bruce Jacob, http://www.ece.umd.edu/~blj/

This paper describes an out-of-order implementation of the 16-bit Ridiculously Simple Computer (RiSC-16), a teaching ISA that is based on the Little Computer (LC-896) developed by Peter Chen at the University of Michigan.


via pdxjjb on retrocomputingforum

see also the web pages at The RiSC-16 Architecture
Quote:
This page includes documentation on the instruction set and several different processor implementations, including sequential, pipelined, and out-of-order. Verilog for the out-of-order core is also available for download. Verilog for the other implementations is not available, because those are projects that I assign to my architecture students.
Mon Mar 09, 2026 5:10 pm
robfinch

Joined: Sat Feb 02, 2013 9:40 am
Posts: 2488
Location: Canada
Post Re: "An Out-of-Order RiSC-16"
The paper is a good place to start and there is even code for an simulation. It should not take much to turn into something running in an FPGA or similar.
I found it helped me get started with OoO designs.

The code is written for understandability as one module. It could be modified to use 'for' loops in some spots, and broken into more modules for something less pedantic.

_________________
Robert Finch http://www.finitron.ca
Thu Mar 12, 2026 11:09 pm WWW
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