Ben's Design of a simple cpu 20 bits wide, with two 8 bytes per word.
Random logic design with TTL or LS TTL. The ALU makes use of the off
state on the 74x170 ram to give 0 on the A alu input.The B input
is active high but the ALU is active low. Only A few data sheets(74F181)
show this mode. Front panel and interupt logic not included.The alu mode
is the a simple decode of the 181 operands, undefined at the moment but
ADD/SUB and logic. Alu operations are ADD,INC A,and alu OPERATION.
28C16's EEPROM are used the top 4k address space to emulate core memory
as a front panel write operation. Regular static memory is used elseware.

Table #1 Instructions
M= MEM B=BYTE J=JUMP S=STORE  !M&B IS SHIFT
[M:B:J:S][ALU][AC:IX][####][####]       : OPCODE
Table #2 state cycle

 A IX+# -> MAR                          / EFA (WRITE BACK CYCLE CORE) FETCH
 B AC   -> OUT  READ/(WRITE ON STORE)   / CORE MEMORY READ OR NEW DATA
                TEST AC ON JMP          / WRITE BACK OR DATA WRITE BACK
                SAVE AC TO A FOR JUMP AND SAVE  / INPUT DATA (BYTE CLEAR 20..9)
       
 C PC+1 -> MAR                          /
   PC=# -> MAR FOR JMP                  / EFA FETCH

 D AC   -> OUT  IF OP AC=AC+OP          / INPUT DATA (CLEAR 20..9)
                ELSE INC
                IF SHIFT AC=AC SHIFT
                IF SET ACC ON CC CY IN is 1

Table #3 C is ac with carry
 REG FILE  IX
 0 C(PC)   PC(PAGE)
 1 A       Z
 2 X       X
 3 S       S
Table #4 is the alu bit slice repeated 5x ic's 1 thru 6
The 74ls298 could be replaced with another 74ls157 and 74ls175 D f/f.


          IC1        IC2        IC3          IC4       IC5

 BUS IN  |INPUT| --@|ALU|  -- |MULX SHIFT|--|2/1  |--@[BUFFER]OUT BUS
 LOAD/CLR|REG  |   +|   |   +-------------- |REG  |+---
                   |                                  |
          IC6      |                                  |
       +-|RAM]---- +    4 BIT ALU SLICE               |
       | |O/C|                                        |
       +----------------------------------------------+
IC1 74LS161 IC2 74LS181 IC3 74LS157 IC4 74LS298 IC5 74LS38 IC6 74LS170
IC31 74LS00

Table 4 is a core style memory with a close idea
of gate delays.

  MEMORY CYCLE CORE STYLE  1.8 US
  300 NS CLOCK .9 US HALF MEMORY CYCLE
  ####________####________  CLOCK A
  ____####________####____  CLOCK B
     <READ>      <WRITE>
  <600 NS OUT><600 NS MAR>
           <IN>

Interupts just clear the PC some how
after clearing the IR register. The idle
state also clears the ir for the front panel.
Adress load,deposit and examine as well as run/stop.

To summerize A Simple design makes use of a wide word length,
indexing and MSI TTL that came out in early 1970's.